Commit Graph

11534 Commits

Author SHA1 Message Date
Tomasz Leman ddf70fa033 config: ace: enable clock gating
This patch enables clock gating in configurations of a ace platforms.

With CONFIG_ADSP_IDLE_CLOCK_GATING enabled clock gating is always
enabled during WAITI.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-12-15 17:07:46 +02:00
Tomasz Leman 9d42bdee8d west.yml: update zephyr to 0a7251e365a
Total of 74 commits.

Changes include:

0a7251e365a xtensa: mmu: Fix tlb shootdown
a19d415c350 xtensa: mmu: Fix xtensa_ptevaddr_get
7382d7052b5 xtensa: mmu: Fix partition permission
b5ca7a06b43 pm: device_runtime: Add delay to async put
0ea173b7747 pm: device_runtime: Avoid unnecessary resume/suspend
3732aae0e07 intel_adsp: power: clock gating in idle
9d1a6b6db5a arch: xtensa: rename expection header

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-12-15 17:07:46 +02:00
Andrula Song 3f572b8cb6 Audio: ASRC: Fix the IPC3 incompatible pointer type
Fix the IPC3 incompatible pointer type passing 'struct
timestamp_data *' to parameter of type 'struct dai_ts_data *',
which is found by ./scripts/fuzz.sh test.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-15 16:16:43 +02:00
Andy Ross 7e5d40aaf7 component: pipeline: Refactor direction testing in pipeline propagation
Clean up some cut/paste code that had spread around, replacing it with
a simpler "comp_same_dir()" predicate.  No behavioral changes, just
refactoring.

Also remove the big comment that was repeated in triplicate.  It
explained this as error handling (i.e. it must be broken topology from
which we want to recover), but in fact cross-pipeline widget
connections in modern SOF do run in opposite directions (c.f. echo
cancellation, which need to look at the output stream to process
microphone input, or smart amp devices that do the reverse).

So just explain it as policy: we don't propagate across
opposite-direction pipelines, period.  Usages that need them need to
manage their pipeline lifecycles manually.

Signed-off-by: Andy Ross <andyross@google.com>
2023-12-15 16:13:16 +02:00
Rander Wang 68c63571fd lmdk: add dummy loadable smart amp support
It will be built will __SOF_MODULE_SERVICE_BUILD__ enabled

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-15 09:46:37 +00:00
Rander Wang 73317455bf dummy-smart-amp: use sink & source buffer
Use process instead of process_audio_stream for pipeline 2.0

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-15 09:46:37 +00:00
Guennadi Liakhovetski 7f1193c11d module-adapter: allow multiple processing modes to be implemented
The module-adapter API has 3 processing modes: raw, stream and
source-sink, and until now only one of them can be implemented by any
module. However, the "modules" module, that loads loadable modules,
has to implement all of them to be prepared to handle any loadable
modules. This adds support for such modules.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-15 09:46:37 +00:00
Guennadi Liakhovetski 3cdbffb11c module: fix firmware compilation for loadable modules
Set correct source & sink parameters for module prepare function

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-15 09:46:37 +00:00
Guennadi Liakhovetski 2c450e69fa loadable module: don't define PHDR twice
Loadable modules are linked, using a linked script, built by a cmake
script. That linker script includes multiple existing linker script
fragments. Each of those fragments defines 1 or more sections and
respective PHDRs. However, some of those scripts, e.g.
common_rodata_linker_script.txt and data_linker_script.txt add
sections to the same rodata_phdr PHDR. This makes the linker
allocate sections in that PHDR twice in the resulting output file:
one copy is real and the other one is filled with zeros. Removing
one of the PHDR definitions solves the problem and removes about
60KiB of empty space from the output file.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-15 09:46:37 +00:00
Marc Herbert c0a8881729 debug_overlay.conf: temporarily disable SOF_BOOT_TEST
- This test has failed on MTL since it was enabled.  Running tests that
  we systematically ignore the failure of is much worse than not running
  them because it provides a false impression of quality.

- This can cause DSP panics as seen in
  https://github.com/thesofproject/sof/pull/8621

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-14 17:40:05 +02:00
Rander Wang 5d1f8b43ca module_adapter: remove redundant sink & source update in prepare for
ipc4

They are done in bind & unbind(). But we need to keep it for ipc3.

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-14 12:48:46 +02:00
Rander Wang 994aec92c1 module: prepare sink & source in bind & unbind function
Module will update source & sink information when bind & unbind
event happen.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-14 12:48:46 +02:00
Daniel Baluta af3fa413cb xtensa-build-zephyr.py: Re-add imx8ulp to -all
This re-adds imx8ulp to --all platform list. This was removed
in commit 7737efadf4 ("xtensa-build-zephyr.py: remove imx8ulp from --all")

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2023-12-14 11:42:21 +02:00
Daniel Baluta 45cbf04949 .github/zephyr: Upgrade to Zephyr SDK 0.16.4
This adds support for imx8ulp.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2023-12-14 11:34:12 +02:00
Daniel Baluta b671eca891 workflows: Upgrade docker container to v0.26.6
This brings in Zephyr SDK 0.16.4 containing toolchain for imx8ulp.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2023-12-14 11:34:12 +02:00
Marc Herbert 3e09f233a4 set_xtensa_params.sh: add ZEPHYR_TOOLCHAIN_VARIANT
This helps with Zephyr and does not hurt anyone else.

Adjust rebuild-testbench.sh accordingly.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-13 22:17:35 +02:00
Marc Herbert 7b8068963c scripts: rename XTENSA_TOOLS_VERSION to TOOLCHAIN_VER as in Zephyr
Rename the variable name used by SOF script with the one expected by the
Zephyr build system for simplicity and consistency.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-13 22:17:35 +02:00
Baofeng Tian ded7ed83dc Audio: mixer: move mixer header file to module folder
This is a clean up, purpose is declutter headers, toml files,
Readme.md etc per module basis, since today everything is scattered
in current code base.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-13 14:24:01 +00:00
Rander Wang c3ba7e462f module_adapter: build params first then verify it
We need to build params based on module base config first then we can
verify it since the income params is built for the source of the this
module. In comp_verify_params the params is applied to buffer so the
sequence is vital. And also remove redundant stream_param set.

Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-12-13 15:38:53 +02:00
Laurentiu Mihalcea aaff352314 topology1: pipe-volume-capture.m4: Set minimum number of channels to 2
Currently, the minimum number of channels for the capture PCM
is set to the same value as the maximum number. This restricts
the number of channels supported by the PCM to the maximum number.
This is wrong if we want to allow arecord to work with multiple channel
values. As such, follow the example of "pipe-volume-playback.m4" and
introduce a new macro: LOCAL_CHANNELS_MIN. This will be set to
"CHANNELS_MIN" if said macro is defined, otherwise it will be set to
2.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-12-13 15:26:16 +02:00
Marc Herbert d661aadd7c xtensa-build-zephyr.py: don't pass -c $plat.toml to rimage
Let west/sign.py find the appropriate .toml file.

This prepares for .toml modularization #8490

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-12 23:50:40 +02:00
Marc Herbert ded019bd46 xtensa-build-zephyr.py: remove IPC3/IPC4 "cavs" switch
Rename:
- tgl-cavs.toml   to tgl.toml
- tgl-h-cavs.toml to tgl-h.toml

Remove the IPC3/IPC4 switch added by commit 6f71808e3e
("xtensa-build-zephyr.py: add ipc4 build support for tgl")

This brings back consistency which is required for the .toml
split (#8490)

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-12 23:50:40 +02:00
Marc Herbert 79e5080175 rimage: remove obsolete, IPC3 tgl.toml and tgl-h.toml
The main branch hasn't supported IPC3 for tgl for a long time.

Follow-up to commit a17c2823d3 ("xtensa-build-zephyr: remove ipc
option")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-12 23:50:40 +02:00
Jyri Sarha f064c029cc topology2: pipeline: Remove rate attribute and rate and channels values
Remove the rest of channels and rate attribute values from pipeline
instamces and remove rate attribute definition from
pipeline-common.conf. There was no channels attribute definition in
pipeline-common.conf, not to mention *_min and *_max attributes.

Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
2023-12-12 20:18:02 +02:00
Jyri Sarha d6999c590e topology2: pipelines/cavs: Remove channels and rate pipeline attribute values
This commit removes all defined values for rate, rate_min, rate_max,
channels, channels_min, and channels_max, from all pipeline
definitions under include/pipelines/cavs. The commit also removes them
from the usage examples in the comments.

The removed pipeline level attribute values are obsolete.

Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
2023-12-12 20:18:02 +02:00
Kai Vehmanen 267d069251 west.yml: update Zephyr to ffd716b4a214
Update Zephyr to bring in total of 290 commits, including
the following related to SOF targets:

0ebeca2eb7d0 intel_adsp: ace: add firmware loading tool
0e73c225bb54 drivers: ssp: Reverted CPA check condition

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-12-12 10:33:56 +02:00
Seppo Ingalsuo 240cc9786a Audio: Module adapter: Fix return value when no prepare operation
The build of testbench for MTL platform simulation causes this build
fail (rebuilt-testbench -p mtl):

src/audio/module_adapter/module/generic.c:213:6:
error: variable 'ret' is used uninitialized whenever 'if'
condition is false [-Werror,-Wsometimes-uninitialized]
        if (md->ops->prepare) {
            ^~~~~~~~~~~~~~~~

src/audio/module_adapter/module/generic.c:236:9:
note: uninitialized use occurs here
        return ret;
               ^~~

Since it's a possibility to have a module without prepare()
operation, the initialize to zero is added to avoid the
return of undefined value.

Reported-by: Marc Herbert <marc.herbert@intel.com>
Signed-off-by: shastry <malladi.sastry@intel.com>
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-11 17:58:16 +00:00
Adrian Bonislawski fd61ed6151 rimage: elf: fixed error handling from file operation
Fixes error handling

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski 63f958e90c smex: elf: fixed error handling from file operation
Fixes commit #e5f337ba70a5

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski e30fedc992 rimage: file_simple: remove dead code
remove logically dead code

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski c1bd155f43 smex: ldc: check fwrite status
Check fwrite status for error

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski 17c226b683 rimage: ext_manifest: check fwrite status
Check fwrite status for error

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski 0f72917521 rimage: ext_manifest: fix fwrite arguments
this will fix parameter order to: size, count

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski c0092bbf7a smex: elf: find_section: check section ptr
Validate section ptr

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Adrian Bonislawski 7501b2e094 smex: elf: remove unnecessary module double free
read module function should only read module,
additional free operation could result in double free scenario

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2023-12-11 17:03:31 +02:00
Baofeng Tian ae464443c8 Audio: mux: split mux code with ipc3 and ipc4
This is a clean up, purpose is de-cluster headers, toml files,
Readme.md etc per module basis, since today everything is
scattered in current code base.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-11 14:08:50 +02:00
Baofeng Tian 11a806bffe Audio: mux: move mux header file to mux module folder
Move mux header file to mux module folder.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-11 14:08:50 +02:00
Andrula Song bfb67801a9 Audio: ASRC: Make HiFi4 share c source files with HiFi3
Make HiFi4 share c source files with HiFi3.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-11 13:10:12 +02:00
Andrula Song 7494ee7e83 Audio: ASRC: Split IPC version code to speclfic file
Move IPC3 related code to asrc_ipc3.c and IPC4 related code
to asrc_ipc4.c.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-11 13:10:12 +02:00
Andrula Song bdf2b6214c Audio: ASRC: Use typedef to replace IPC version asrc cfg
Use typedef ipc_asrc_cfg to replace the splited IPC version
asrc module config structure.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-11 13:10:12 +02:00
Andrula Song 0ff7c1be3a Audio: ASRC: Move header files into ASRC folder
Move the ASRC related header files into ASRC folder.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-11 13:10:12 +02:00
Adrian Warecki 7a63f66961 rimage: Introduce ALIGN_UP macro
Created ALIGN_UP macro to simplify calculations.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-12-11 12:38:39 +02:00
Adrian Warecki e91f077a52 rimage: manifest: Use DIV_ROUND_UP macro
Used DIV_ROUND_UP macro to calculate page count.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-12-11 12:38:39 +02:00
Adrian Warecki d8113fabc9 rimage: Limit input module count to module array size
Added limit of a number of input modules provided in a command line to the
maximum number of supported modules (size of module array / MAX_MODULES)

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-12-11 12:38:39 +02:00
Yong Zhi a108c5e940 topology2: Remove pcm cap attributes
Remove the attributes that do not belong to Pipeline class.
There are no changes to compiled binary.

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
2023-12-11 12:13:21 +02:00
Marc Herbert 3b8d872619 xtensa-build-zephyr.py: untabify XCC installation in --help message
This was broken from the start when converting the script from shell
script to Python.

A good reference was left in the non-Zephyr script which is still
active: `./scripts/xtensa-build-all.sh -h`

Fixes initial commit 1de3ef3675 ("Rewritten xtensa-build-zephyr.sh to
python")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-11 12:06:40 +02:00
Yong Zhi cdd1c91608 topology2: google-rtc-aec: Add Byte control
Add binary controls for AEC tuning data with
max size set to 2048.

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
2023-12-08 15:29:31 +02:00
Guennadi Liakhovetski dba33ccbfd vmh test: extend test for spanning
Test both cases - when spanning multiple blocks is allowed and when
it isn't.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-08 15:29:06 +02:00
Guennadi Liakhovetski ee534b2203 test: extend VMH testing with an allocation
Add calls to vmh_alloc() and vmh_free() for testing.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-08 15:29:06 +02:00
Guennadi Liakhovetski c8ecb88355 test: add a simple VMH test
This adds an initial Virtual Memory Heap test.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-08 15:29:06 +02:00