Reverts all previosly changed cAVS pipelines from 3 to 2 periods.
Now we have separate buffers for DMA, so there is no need to make
DAI buffers consist of 3 periods. DMA will take care of any internal
hardware requirements.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Switches all pipelines for cAVS platforms to timer scheduling.
This way we limit the number of interrupt levels processed
in the system. Timer, IPC and IDC are already on level 2 and
DMAs are on level 5.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Changes number of SSP and DMIC DAI periods from 2 to 3.
This way we can support both timer and new single DMA
channel scheduling.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Currently having different amount of periods between DAI and the
component before it is not allowed. This is because it is not allowed to
resize dma connected buffers. So make 50kHz topology use src-volume
pipeline, which has additional volume component, which in turn has
correct amount of periods for the DAI connection.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
Tomasz Lauda