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Author SHA1 Message Date
Jaroslaw Stelter 0f25a31089 ptl: Add FPGA overlay configuration 
Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
 2024-06-24 16:15:41 +02:00