mirror of https://github.com/thesofproject/sof.git
ptl: Add FPGA overlay configuration
Add PTL configuration changes required to build FW for FPGA. After next SOF rebase default target will be build for RVP, so for FPGA we will use configuration overlay. Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
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CONFIG_DAI_DMIC_HW_IOCLK=19200000
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