From 0f25a3108913a27e2ae232102c4fc7acfd6dd252 Mon Sep 17 00:00:00 2001
From: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Date: Thu, 25 May 2023 13:16:29 +0200
Subject: [PATCH] ptl: Add FPGA overlay configuration

Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
---
 app/overlays/ptl/fpga_overlay.conf | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 app/overlays/ptl/fpga_overlay.conf

diff --git a/app/overlays/ptl/fpga_overlay.conf b/app/overlays/ptl/fpga_overlay.conf
new file mode 100644
index 000000000..1d09ecb6b
--- /dev/null
+++ b/app/overlays/ptl/fpga_overlay.conf
@@ -0,0 +1,3 @@
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
+CONFIG_DAI_DMIC_HW_IOCLK=19200000
+