Commit Graph

11586 Commits

Author SHA1 Message Date
Kalva, DineshKumar 9824a05d7c dma-copy: remove CONFIG_DMA_GW macro.
Remove CONFIG_DMA_GW macro to use dma_copy_set_stream_tag function
to get dma channel on AMD platforms for probe.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
2024-01-03 10:27:01 +02:00
Kalva, DineshKumar b9d0d86e46 probe: small fixes in probe functionality.
local dma_sg_config is not required,
struct probe_dma_ext holds the DMA config segments.

proper fix for notifier_unregister to remove the probe point functionality.

Signed-off-by: Kalva, DineshKumar <dineshkumar.kalva@amd.com>
2024-01-03 10:27:01 +02:00
Peter Ujfalusi 98cc1d3da3 xtensa-build-zephyr.py: Add arl-s alias to mtl platform
ARL-S is using the same debugkey/community key binary as MTL.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2024-01-02 12:35:14 +02:00
Jaroslaw Stelter d66ad570e8 iadk: module_adapter: Fix return code for IADK proc
IADK processing module interface uses uint32_t return code
while cSOF is using int type. This patch checks return value
from processing() method and returns -ENODATA in case of
failure.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-12-22 13:53:13 +02:00
Jaroslaw Stelter d4bed3df83 iadk: module_adapter: Check return code for sink/source
Add check of return code for sink/source api functions.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-12-22 13:53:13 +02:00
Baofeng Tian b617388c62 rimage: mtl: add copier and eq-iir CPC cases
Copier missed ibs(384)/obs(192) case, and eq-iir missed
ibs(384)/obs(384) case, adding it to current CPC config for mtl.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-22 12:55:29 +02:00
Kai Vehmanen a9bd8245d2 topology2: cavs-nocodec-bt: fix PCM0 and PCM1 capabilities
The pipelines for PCM0 and PCM1 only support S32_LE audio
format. Fix the PCM capability descriptions to match the actual
pipeline definitions. This allows to run test suites that enumerate
all support PCMs and their formats.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-12-22 11:36:39 +02:00
Serhiy Katsyuba 2a0607c658 ipc4: Regression FIX: Do not clear sources/sinks on reset
After https://github.com/thesofproject/sof/pull/8594 been merged, sources
and sinks are now setup on .bind() and .unbind(). Previously they were
setup in .prepare(). However, there were code left in
module_adapter_reset() which clears sources and sinks arrays. That broke
some tests: modules which use source/sink API stopped working correctly
after pipeline reset.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-12-21 16:03:26 +00:00
Seppo Ingalsuo dabf0a672e Tools: Topology2: Add switch control to topologies with DRC
The mixer control for switch is added to widget definition
of drc.conf.

In cavs-mixin-mixout-efx-hda.conf the existing control name
is changed to have "bytes" similarly as multiband-drc has. The
switch control is added for the widget to implement the switch.

The controls definitions files in benchmark topologies are replaced
to new format from current .conf generator script. The bytes control
is same as before, and the mixer control for switch is added.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-21 13:12:42 +00:00
Seppo Ingalsuo 439d69c155 Audio: DRC: Add processing enable switch control
This patch adds to DRC component in IPC4 mode a control to
switch processing on/off. The control is useful for DRC
pipeline that is used for both headphone (unprocessed) and
speaker (processed). It also allows the user to switch off
DRC processing if desired.

If a blob has enable set to false the processing cannot be
enabled with the switch control. If the blob enables processing,
the user space can control processing on or off.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-21 13:12:42 +00:00
Guennadi Liakhovetski cf9a444bfc toml: modularise TOML configuration
Split TOML configuration files into platform and module parts. Use
the C preprocessor to merge them back together.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-12-21 13:07:13 +00:00
Serhiy Katsyuba 60212cf387 ipc4: mixin/mixout: Fix naming after channel remapping removal
Previously when channel remapping was supported processing was done
iterating by frames. After channel remapping was removed processing
was changed to iterate by samples, however, for some reason the code
still uses confusing "frame" variables.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-12-20 19:49:50 +02:00
Serhiy Katsyuba e9ab25ba2a ipc4: mixin/mixout: Simplify naming after remapping mode been removed
Previously we had "normal" and "channel remapping" modes. Since channel
remapping mode was removed, "normal" is the only supported mode, no need
to prepend names with "normal".

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-12-20 19:49:50 +02:00
Serhiy Katsyuba e7375aacd1 ipc4: mixin/mixout: Remove redundant mute channel impl
Mute channel functionality was previously used as part of channel
remapping feature. Since that feature was removed some time ago mute
channel functionality is no longer used and is just a leftover from not
fully completed cleanup.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-12-20 19:49:50 +02:00
Andrula Song 7ec22d80ea Tools: Topology: Fix the topology2 ASRC UUID
Correcting the UUID in asrc.conf to match with firmware.

Signed-off-by: Andrula Song <andrula.song@intel.com>
2023-12-20 14:58:58 +00:00
Marcin Szkudlinski 4fb1090c54 DP: LL module should get 1ms data chunk in each cycle
DP may produce a huge chunk of output data (i.e. 10 LL
cycles), and the following module should be able to
consume it in 1 cycle chunks, one by one

unfortunately LL modules are designed to drain input
buffer
That leads to issues when DP provide huge data portion

FIX: copy only the following module's IBS in each LL cycle

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2023-12-20 14:51:00 +00:00
Kai Vehmanen 486ccfe7bb west.yml: upgrade Zephyr to a1042c40796
Update Zephyr to bring in total of 169 commits, including
the following related to SOF targets:

dab6f665ca77 xtensa: fix build errors with cache functions
039e5ef1b813 intel_adsp: remove rimage sign() from `west flash`
c7e3ccd51ad4 drivers: dma: intel_adsp_gpdma: fix issue with stop and PM refcounts

Link: https://github.com/thesofproject/sof/issues/8503
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-12-20 14:12:55 +00:00
Dobrowolski, PawelX 4f028c5ca3 up_down_mixer: sink/source refactor
module being refactored to use sink/source API

Signed-off-by: Dobrowolski, PawelX <pawelx.dobrowolski@intel.com>
2023-12-19 18:47:38 +00:00
Marcin Szkudlinski 3d4883a655 DP: provide data to next LL module no earlier than DP deadline
lets assume DP with 10ms period (a.k.a a deadline).
It starts and finishes earlier, i.e. in 2ms providing 10ms of data
LL starts consuming data in 1ms chunks and will drain
10ms buffer in 10ms, expecting a new portion of data on 11th ms

BUT - the DP module deadline is still 10ms,
regardless if it had finished earlier and it is completely fine
that processing in next cycle takes full 10ms - as long as it
fits into the deadline.

It may lead to underruns:

LL1 (1ms) ---> DP (10ms) -->LL2 (1ms)

ticks 0..9 -> LL1 is producing 1ms data portions,
             DP is waiting, LL2 is waiting
tick 10 - DP has enough data to run, it starts processing
tick 12 - DP finishes earlier, LL2 starts consuming,
          LL1 is producing data
ticks 13-19 LL1 is producing data,
            LL2 is consuming data (both in 1ms chunks)
tick 20  - DP starts processing a new portion of 10ms data,
           having 10ms to finish
	      !!!! but LL2 has already consumed 8ms !!!!
tick 22 - LL2 is consuming the last 1ms data chunk
tick 23 - DP is still processing, LL2 has no data to process
	 			!!! UNDERRUN !!!!
tick 19 - DP finishes properly in a deadline time

Solution: even if DP finishes before its deadline,
the data must be held till deadline time, so LL2 may
start processing no earlier than tick 20

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
2023-12-19 18:29:22 +00:00
Jaroslaw Stelter 0bf03093f0 iadk: module_adapter: Switch IADK modules to use source/sink
The IADK libraries should support source/sink interface. This patch
changes IADK adapter part to implement source/sink interface.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-12-19 18:17:41 +00:00
Baofeng Tian 9a906586d1 Audio: drc: remove incompatible inline for three functions
These three functions are called by external modules and its prototype
is not defined with inline, also these functions are not performance
critical function, no need inline.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-19 17:21:53 +00:00
Baofeng Tian d360607963 audio: drc: move drc header file from include path to module folder
This is a clean up, purpose is declutter headers, toml files,
Readme.md etc per module basis, since today everything is scattered
in current code base.

Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
2023-12-19 17:21:53 +00:00
Seppo Ingalsuo 3d083e7ca7 Tools: Tune: DRC: Add calculation of blob for speaker processing
This patch adds generation of a blob that applies about
10 dB gain with compression and additional post gain of
3 dB for strong loudness boost effect.

The drc_gen_coefs.m script is changed to display
the master linear gain as decibels to help achieve
suitable gain when setting parameters.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Seppo Ingalsuo 18f170352d Tools: Tune: DRC: Add information how to create topology blobs
This patch updates the generator script example_drc.m with added
information how the blobs were created.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Seppo Ingalsuo 4baa131628 Tools: sof-ctl: Add DRC blobs for testing
These blobs are useful in setting DRC in runtime to
pass-through or strong compression mode to evaluate
performance.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Seppo Ingalsuo 895450ec6f Tools: Topology2: Update comments in DRC configuration blobs
Add descriptive comments how these blobs for DRC were
created.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Seppo Ingalsuo b2b6f099d2 Tools: Topology2: DRC: Add blob for speaker processing
This blob exercises fully the features of DRC and is
therefore useful for performance evaluation in all
operation regions.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Seppo Ingalsuo 6eed29c74f Tools: Topology1: Add speaker DRC blob for testbench run
This blob exercises fully the features of DRC and is
therefore good for testbench runs to evaluate performance
in all operation regions.

The pipeline pipe-drc-playback.m4 is used only with testbench
so it is safe to change to use this blob.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:18:44 +00:00
Kai Vehmanen 725c7d98a7 app: debug_overlay: enable CONFIG_DAI_VERBOSE_GLITCH_WARNINGS
Enable the DAI verbose glitch warnings in the debug builds.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-12-19 17:10:18 +00:00
Kai Vehmanen c17bc039a6 audio: dai-zephyr: put no-data checks behind a build option
Put the data availability checks behind a build option (new option
CONFIG_DAI_VERBOSE_GLITCH_WARNINGS). In normal conditions, the DAI copy
should never be called in a condition when there is no data to be
copied. The audio interface is running and needs a constant stream of
audio samples, so there is no remedy for not having data. In practise,
most of the DAIs have a small buffer and can survive transient small
gaps in data flow.

The existing code has warning level logs for this condition. This is
very useful for debug, as many common problems in firmware (and DSP
topologies) show up as delays observed in the DAI copy logic. For
product use, printing the warnings may make the situation worse by
increasing the DSP load at a time when it has just missed a deadline.

To allow for both debug and to avoid these checks in product
builds, move the related checks behind a separate build option.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-12-19 17:10:18 +00:00
Balamurugan C fc860826a8 topology2:cavs-es83x6: Add support to Es8326 codec + HDMI-in capture
Add Es8326 codec support and HDMI-in capture via I2S.

Signed-off-by: Balamurugan C <balamurugan.c@intel.com>
2023-12-19 17:03:57 +00:00
Peter Ujfalusi 1adb1e45d3 xtensa-build-zephyr.py: Add option to create deployable build
The default firmware file path is standardized among vendors as follows:
IPC3
    /lib/firmware/VENDOR/sof/
    ├── community
    │   └── sof-PLAT.ri
    ├── dbgkey
    │   └── sof-PLAT.ri
    └── sof-PLAT.ri
IPC4
    /lib/firmware/VENDOR/sof-ipc4/
    └── PLAT
        ├── community
        │   └── sof-PLAT.ri
        ├── dbgkey
        │   └── sof-PLAT.ri
        └── sof-PLAT.ri\n

Currently the binaries created by the build can only be used for direct
deployment on IPC3 platforms but if one builds different vendor firmwares
the files have to be manually picked and sorted out.
We have two flags: --fw-naming and --use-platform-subdir which can be
played with but still not going to produce deployable build.

Introduce a new flag: --deployable-build
With the flag specified all other modificators are going to be ignored and
the build will do the 'right thing' to create a directory structure which
can be deployed as it is to the target's firmware directory.

To achieve this several changes needed:
PlatformConfig:
- drop the name member and replace it with a vendor string
- add a flag to indicate IPC4 platforms
  Later a new option can be added if needed for platforms which can be
  IPC3 or IPC4

Ignore fw-naming and use-platform-subdir in case of deployable build. The
options will be reset to their default in case they are changed.

symlink_or_copy extended to handle relative symlinks when the target and
link is not under the same directory.

The --deployable-build is disabled by default, it has to be enabled to
create deployable build for now.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2023-12-19 17:02:38 +00:00
Peter Ujfalusi 7e42c43c21 xtensa-build-zephyr.py: Print out the platform aliases in help
Print platform alias information to reduce the need for guessing when
trying to figure out what platform supports what platform.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2023-12-19 17:02:38 +00:00
Peter Ujfalusi 38d447f3f9 xtensa-build-zephyr.py: Fill in missing platform aliases
The following aliases are missing:

tgl: adl-n, rpl
tgl-h: rpl-s
mtl: arl

Update the aliases list accordingly.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2023-12-19 17:02:38 +00:00
Peter Ujfalusi 4d0da9896b xtensa-build-zephyr.py: Remove IPC4_CONFIG_OVERLAY from PlatformConfig
The IPC4_CONFIG_OVERLAY is no longer used, remove it.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2023-12-19 17:02:38 +00:00
Marc Herbert 38a730b9c9 rebuild-testbench.sh: add incremental build command in help message
Add interactive menuconfig and incremental build commands in help
message of rebuild-testbench.sh

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:54:45 +00:00
Marc Herbert 27e5f40b9a rebuild-testbench.sh: error when unknown arguments are passed
Silently discarding user input is really bad.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:54:45 +00:00
Marc Herbert acc4f672db rebuild-testbench.sh: use cmake -B to simplify rebuild_testbench()
Cosmetic change.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:54:45 +00:00
Marc Herbert caf28abbcd rebuild-testbench.sh: rename BUILD_TESTBENCH_DIR to TESTBENCH_DIR
It's a source directory, not a build directory.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:54:45 +00:00
Marc Herbert 954b862017 rebuild-testbench.sh: move all constants at the top
Cosmetic change.

Also exit 0 when using -h; it's not a crime!

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:54:45 +00:00
Marc Herbert de28dd5fe5 Give fuzz.sh a `proper -h` help text
Long overdue.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:52:33 +00:00
Marc Herbert 03fe9d3149 fuzz.sh: use set -x to make the `west build ...` command visible
Users want to know what exactly failed.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:52:33 +00:00
Marc Herbert b7df375a33 .github/fuzz: add -DEXTRA_CFLAGS='-Werror' -DEXTRA_CXXFLAGS='-Werror'
We want to catch warnings like the incompatible pointer warning fixed by
3f572b8cb6 ("Audio: ASRC: Fix the IPC3 incompatible pointer type")

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-19 16:52:33 +00:00
Seppo Ingalsuo e5da161264 Tools: Topology2: Add sof-hda-benchmark-rtnr16/24/32-<platform>
This patch adds build of hda-generic development topologies to
test IGO NR component with all s16/s24/s32 formats.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:41:02 +02:00
Seppo Ingalsuo 8df176a7bb Tools: Topology2: Add widget class IGO NR
This patch allows to build topologies to use the IGO NR
component.

Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2023-12-19 17:41:02 +02:00
Fabiola Kwasowiec b3b9abffe7 base_fw: add DMI_FORCE_L1_EXIT FW config
Add new parameter for SW to force DMI L1 exit on IPC request.

Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
2023-12-18 18:17:14 +02:00
Fabiola Kwasowiec fb06e4d4cd west: zephyr update
intel_adsp: lnl: add missing definition for lnl
28d5d23a232b69b213112e723e0a6392cbd5a47e

Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
2023-12-18 18:17:14 +02:00
Daniel Baluta 479bd7a5eb .github/zephyr: Add imx8ulp target to CI
Now that imx8ulp support is ready with Zephyr add it as compilation
target for CI.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2023-12-18 16:34:24 +02:00
Marc Herbert 3967255a99 .github: run all workflows in daily tests
Not sure why we didn't do this sooner

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-18 15:48:21 +02:00
Marc Herbert 22ab28881b .github: make all workflows callable and dispatchable
Because why shouldn't they be.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-12-18 15:48:21 +02:00