With the switch to HWMv2, `CONFIG_SOC_SERIES_MIMX9_A55`
has been renamed to `CONFIG_SOC_MIMX9352_A55` so make sure
we also use the correct name when fetching the driver structure
associated with 93's DMACs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since the EDMA and HOST DMA nodes have been introduced to
the i.MX93 overlay, add entries in the dma array which will
create a struct dma for each of these DMACs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
z_soc_uncached_ptr() / z_soc_cached_ptr() have been removed from
Zephyr and replaced with sys_cache_uncached_ptr_get() and
sys_cache_cached_ptr_get() respectively.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This changes the secondary core power up routine to use the newly
introduced k_smp_cpu_start() and k_smp_cpu_resume(). This removes
the need to mirror part of the SMP start up code from Zephyr, and
no longer need to call into Zephyr private kernel code.
West update includes :
eefaeee061c8 kernel: smp: introduce k_smp_cpu_resume
042cb6ac4e00 soc: intel_adsp: enable DfTTS-based time stamping
on ACE platforms
6a0b1da158a4 soc: intel_adsp: call framework callback function for restore
e7217925c93e ace: use a 'switch' statement in pm_state_set()
c99a604bbf2c ace: remove superfluous variable initialisation
a0ac2faf9bde intel_adsp: ace: enable power domain
4204ca9bcb3f ace: fix DSP panic during startup (fixes c3a6274bf5e4)
d4b0273ab0c4 cmake: sparse.template: add COMMAND_ERROR_IS_FATAL
ca12fd13c6d3 xtensa: intel_adsp: fix a cache handling error
0ee1e28a2f5f xtensa: polish doxygen and add to missing doc
035c8d8ceb4b xtensa: remove sys_define_gpr_with_alias()
a64eec6aaeec xtensa: remove XTENSA_ERR_NORET
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
[guennadi.liakhovetski@linux.intel.com: update Zephyr hversion]
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Clean up an incorrect TODO comment in the power management runtime
policy.
The removed comment suggested the need for substates to handle cases where
power gating (PG) is enabled and clock gating (CG) is disabled. However,
this is not accurate because:
- Enabling PG when CG is not allowed is not feasible; entering PG could
inadvertently gate the clock even if CG prevent is active.
- Substates are no longer required as clock gating is now always enabled.
This change clarifies the power management behavior and removes confusion
around the handling of power and clock gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Allocation sizes were calculated with faulty logic. Bits to check
size calculation is not needed since array position was calculated
and loop should go from this position to array end.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
When allocating non contiguously if exact block size was allocated on
given physical allocator it would fail. Fix logic to include
that event.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Keep timer interrupt handling on the primary core, this avoids
secondary cores failing to handle timer interrupts immediately after
power on.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Replace a potentially infinite loop with one, using a retry counter
to avoid lock ups.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
For rballoc_allign() call when caps are not correct it is
enough to return error. k_panic() call is not required here.
Previous change exposed this issue:
https://github.com/thesofproject/sof/issues/8832,
but it is sufficient to log error and return NULL at this point.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
L3_HEAP is used in library manager for library storage buffer allocation
and in D3 enter/exit flows to allocate IMR context storage buffer.
Both buffers should be aligned so use rballoc_align() routine to get
correctly aligned buffers.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This patch implements recommended hardware flow for
Intel ACE platforms.
The L3 heap should be accessed via cached pointers
including management data.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Zephyr and XTOS' rtos/interrupt.h already include
drivers/interrupt.h so there's no need to include it again
in files which make use of one of the two rtos/interrupt.h
headers. As such, this commit removes all drivers/interrupt.h
inclusions from said files.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This is a weak stub for the Cadence libc's allocator (which is just a
newlib build). It's traditionally been provided like this in SOF for
the benefit of C++ code where the standard library needs to link to a
working malloc() even if it will never call it.
Longer term this should be integrated as a working allocator, either
unified with the one here or in the Zephyr libc layer. Zephyr already
provides a newlib-compatible _sbrk_r(), we just have to tell it to use
it when linking against Cadence libc.
Signed-off-by: Andy Ross <andyross@google.com>
Register pm_state_notifier to set ready_flag for secondary core when it
is powered up for second time after first fw boot. We can remove
CONFIG_ADSP_IMR_CONTEXT_SAVE check for cavs platform for this feature.
Signed-off-by: Rander Wang <rander.wang@intel.com>
The_very_long_variable names make it hard to modify
the code and keep to under-100-characters coding
guidelines of the codebase.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Because module uses SYS_INIT defined in init.h. Things likely worked
because of indirect includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Module is using Zephyr SYS_INIT API, defined in init.h, not device.h.
Code relied on indirect includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When converting #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE to if(IS_ENABLE(
CONFIG_ADSP_IMR_CONTEXT_SAVE), we should use if (!IS_ENABLE() ||
Signed-off-by: Rander Wang <rander.wang@intel.com>
Fix multicore test issue on cavs platforms which don't support context
save now, so need to init cpu when the core boot up.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Add virtual heap allocators that allocate on proper heaps and
map physical memory where nesscessary.
Add free function that frees up the virtual heap memory and
unmaps physical memory when possible.
Virtual heap allocator allows using virtual memory as a base
for allocation and booking memory. Physical memory banks
will be mapped when needed allowing for greater flexibility
with mapping.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Zephyr uses MP_MAX_NUM_CPUS internally to represent the
number of cores available and consequently to allocate
resources. It is even expected, and checked through assert,
that these two symbols have the same value. Use different
value can lead to an undesired behavior, so lets use
MP_MAX_NUM_CPUS.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
During PowerOff (D3) transition Zephyr Power Manager must have
a pointer in IMR to save the LP/HPSRAM memory before
powering off.
As zephyr has no access to IMR heap, the memory must
be allocated by SOF
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
The DSP cannot enter the power gating state if it has not yet received
an ack from host after sending an ipc message.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Informing the primary core that the Idle thread on secondary core is
ready. During the D3 exit flow thread is not initialize again, but
restored from previously saved context.
This patch includes also zephyr version update to aba3b12e31 (total 15
commits). Changes related to intel_adsp contain refactor and fixes for
ACE secondary cores power flows.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Idle thread should be initialize only when core it booting for the first
time. Doing this again would overwrite the kernel structs and the idle
thread stack.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Use zephyr cache APIs instead of xtensa specific ones.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit removes all occurrences of the soc.h header file
since this is not used. This also fixes build problem on i.MX93
caused by the fact that i.MX93 doesn't have a soc.h.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Start using zephyr pm_runtime, clk and dma glue code in cavs25 native
drivers build. Move the files from ace/lib into zephyr/lib.
Also update west.yaml to related zephyr commit as power related
files have been moved to zephyr side.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
The purpose of this commit is to separate the XTOS-specifc
code from the Zephyr-specifc code found in sof/drivers/idc.h.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add virtual memory regions info gathering from zephyr and introduce
structs agregating this information.
Add proper defines for memory management.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This extends the ideas in CONFIG_LIBRARY=y to implement SOF as an
application for the Zephyr native_posix architecture. These are host
x86 or x86_64 binaries that include a full OS build, which can be used
(via mocked drivers) for testing against host validation environments
like ASAN/MSAN.
The mechanism uses the existing "host" architecture used by
CONFIG_LIBRARY, but adds a new platform layer named "posix", populated
entirely with stubs.
No driver integration is provided in this patch. The resulting
executable builds correctly, but has no devices and won't do anything.
Signed-off-by: Andy Ross <andyross@google.com>
L3 memory should support have support
for allocating/freeing memory
A heap support in L3 is introduced by
this commit
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
The heap size def should not be in alloc.c
This is a platform specific setting
Also (unused by now) macros regarding IMR bootloader
have been removed - moved to Zephyr
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
to have more order in the code - move memory code from a huge
common wrapper.c to specific lib/alloc.c
Note there is NO changes in the code, code is as it was before
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Laurentiu Mihalcea