move HPSRAM heap size def to zephyr adsp_memory.h

The heap size def should not be in alloc.c
This is a platform specific setting
Also (unused by now) macros regarding IMR bootloader
have been removed - moved to Zephyr

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>

src/platform/apollolake/include/platform/lib/memory.h

@@ -14,6 +14,11 @@
 #include <cavs/lib/memory.h>
 #include <sof/lib/cpu.h>
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 /* physical DSP addresses */
 
 /* shim */
@@ -110,8 +115,12 @@
 #define ROM_SIZE		0x00002000
 
 /* IMR accessible via L2$ */
+#ifndef L2_SRAM_BASE
 #define L2_SRAM_BASE		0xA000A000
+#endif
+#ifndef L2_SRAM_SIZE
 #define L2_SRAM_SIZE		0x00056000
+#endif
 
 #define L2_VECTOR_SIZE			0x1000
 
@@ -365,7 +374,9 @@
  */
 
 /* LP SRAM */
+#ifndef LP_SRAM_BASE
 #define LP_SRAM_BASE		0xBE800000
+#endif
 
 /* Heap section sizes for module pool */
 #define HEAP_RT_LP_COUNT8		0
@@ -435,6 +446,7 @@
 #define ROM_RESET_LIT_SIZE	0x200
 
 /* boot loader in IMR - APL uses manifest v1.8 and SKL/KBL use v1.5 */
+#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE
 #if CONFIG_APOLLOLAKE && !(CONFIG_KABYLAKE || CONFIG_SKYLAKE)
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB000A000
 #elif CONFIG_KABYLAKE || CONFIG_SKYLAKE
@@ -442,6 +454,7 @@
 #else
 #error Platform not specified
 #endif
+#endif  /* IMR_BOOT_LDR_TEXT_ENTRY_BASE */
 
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x86
 #define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + \

src/platform/cannonlake/include/platform/lib/memory.h

@@ -15,6 +15,11 @@
 #include <cavs/lib/memory.h>
 #include <sof/lib/cpu.h>
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 /* physical DSP addresses */
 
 /* shim */
@@ -347,7 +352,9 @@
  */
 
 /* LP SRAM */
+#ifndef LP_SRAM_BASE
 #define LP_SRAM_BASE		0xBE800000
+#endif
 
 /* Heap section sizes for module pool */
 #define HEAP_RT_LP_COUNT8			0
@@ -430,7 +437,10 @@
 #define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
 
+#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
+#endif
+
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
 #define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
 					IMR_BOOT_LDR_TEXT_ENTRY_SIZE)

src/platform/icelake/include/platform/lib/memory.h

@@ -15,6 +15,11 @@
 #include <cavs/lib/memory.h>
 #include <sof/lib/cpu.h>
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 /* physical DSP addresses */
 
 /* shim */
@@ -343,7 +348,9 @@
  */
 
 /* LP SRAM */
+#ifndef LP_SRAM_BASE
 #define LP_SRAM_BASE		0xBE800000
+#endif
 
 #if (CONFIG_CAVS_LPS)
 #define LPS_RESTORE_VECTOR_OFFSET 0x1000
@@ -402,7 +409,10 @@
 #define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
 
+#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
+#endif
+
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
 #define IMR_BOOT_LDR_LIT_BASE		(IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
 					IMR_BOOT_LDR_TEXT_ENTRY_SIZE)

src/platform/library/include/platform/lib/memory.h

@@ -13,6 +13,11 @@
 #include <inttypes.h>
 #include <stddef.h>
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 struct sof;
 
 #define PLATFORM_DCACHE_ALIGN	sizeof(void *)
@@ -69,7 +74,9 @@ static inline uint32_t arch_get_stack_size(void)
 #define HP_SRAM_SIZE (SRAM_BANK_SIZE * 47)
 
 #define HP_SRAM_BASE	0xBE000000
+#ifndef LP_SRAM_BASE
 #define LP_SRAM_BASE	0xBE800000
+#endif
 
 #define SOF_FW_END		(HP_SRAM_BASE + HP_SRAM_SIZE)
 

src/platform/meteorlake/include/platform/lib/memory.h

@@ -10,6 +10,11 @@
 #ifndef __PLATFORM_LIB_MEMORY_H__
 #define __PLATFORM_LIB_MEMORY_H__
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 #include <ace/lib/memory.h>
 #include <mem_window.h>
 #include <sof/lib/cpu.h>
@@ -48,6 +53,11 @@
 #define PLATFORM_HEAP_SYSTEM_SHARED	1
 #define PLATFORM_HEAP_BUFFER		2
 
+/**
+ * size of HPSRAM system heap
+ */
+#define HEAPMEM_SIZE 0x40000
+
 #endif /* __PLATFORM_LIB_MEMORY_H__ */
 
 #else

src/platform/suecreek/include/platform/lib/memory.h

@@ -15,6 +15,11 @@
 #include <cavs/lib/memory.h>
 #include <sof/lib/cpu.h>
 
+/* prioritize definitions in Zephyr SoC layer */
+#ifdef __ZEPHYR__
+#include <adsp_memory.h>
+#endif
+
 /* physical DSP addresses */
 
 /* shim */
@@ -332,7 +337,9 @@
  */
 
 /* LP SRAM */
+#ifndef LP_SRAM_BASE
 #define LP_SRAM_BASE		0xBE800000
+#endif
 
 /* Heap section sizes for module pool */
 #define HEAP_RT_LP_COUNT8			0
@@ -429,7 +436,9 @@
 					SOF_STACK_TOTAL_SIZE)
 #define BOOT_LDR_STACK_SIZE		SOF_STACK_TOTAL_SIZE
 
+#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	BOOT_LDR_TEXT_ENTRY_BASE
+#endif
 
 /* code loader entry point for base fw */
 #define _SRAM_VECBASE_RESET (BOOT_LDR_BSS_BASE + BOOT_LDR_BSS_SIZE)

src/platform/tigerlake/include/platform/lib/memory.h

@@ -447,7 +447,10 @@
 #define IMR_BOOT_LDR_MANIFEST_BASE	0xB0032000
 #define IMR_BOOT_LDR_MANIFEST_SIZE	0x6000
 
+#ifndef IMR_BOOT_LDR_TEXT_ENTRY_BASE
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
+#endif
+
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
 #endif
 

zephyr/lib/alloc.c

@@ -69,8 +69,6 @@ __section(".heap_mem") static uint8_t __aligned(64) heapmem[HEAPMEM_SIZE];
 
 #elif CONFIG_ACE
 
-#define HEAPMEM_SIZE 0x40000
-
 /*
  * System heap definition for ACE is defined below.
  * It needs to be explicitly packed into dedicated section