[ABI] IMRheap preparation - add config and flags

Add
 - a kconfig option enabling a heap in L3
 - a memory capability flag SOF_MEM_CAPS_L3
+ small cleanup in whitespaces

Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>

app/boards/intel_adsp_ace15_mtpm.conf

@@ -33,6 +33,7 @@ CONFIG_INTEL_ADSP_TIMER=y
 CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y
 
 CONFIG_HEAP_MEM_POOL_SIZE=8192
+CONFIG_L3_HEAP=n
 CONFIG_RIMAGE_SIGNING_SCHEMA="mtl"
 
 CONFIG_FORMAT_CONVERT_HIFI3=n

src/include/ipc/topology.h

@@ -77,14 +77,16 @@ struct sof_ipc_comp {
 /*
  * SOF memory capabilities, add new ones at the end
  */
-#define SOF_MEM_CAPS_RAM			(1 << 0)
-#define SOF_MEM_CAPS_ROM			(1 << 1)
-#define SOF_MEM_CAPS_EXT			(1 << 2) /**< external */
-#define SOF_MEM_CAPS_LP			(1 << 3) /**< low power */
-#define SOF_MEM_CAPS_HP			(1 << 4) /**< high performance */
-#define SOF_MEM_CAPS_DMA			(1 << 5) /**< DMA'able */
-#define SOF_MEM_CAPS_CACHE			(1 << 6) /**< cacheable */
-#define SOF_MEM_CAPS_EXEC			(1 << 7) /**< executable */
+#define SOF_MEM_CAPS_RAM		BIT(0)
+#define SOF_MEM_CAPS_ROM		BIT(1)
+#define SOF_MEM_CAPS_EXT		BIT(2) /**< external */
+#define SOF_MEM_CAPS_LP			BIT(3) /**< low power */
+#define SOF_MEM_CAPS_HP			BIT(4) /**< high performance */
+#define SOF_MEM_CAPS_DMA		BIT(5) /**< DMA'able */
+#define SOF_MEM_CAPS_CACHE		BIT(6) /**< cacheable */
+#define SOF_MEM_CAPS_EXEC		BIT(7) /**< executable */
+#define SOF_MEM_CAPS_L3			BIT(8) /**< L3 memory */
+
 /*
  * overrun will cause ring buffer overwrite, instead of XRUN.
  */

src/include/kernel/abi.h

@@ -29,7 +29,7 @@
 
 /** \brief SOF ABI version major, minor and patch numbers */
 #define SOF_ABI_MAJOR 3
-#define SOF_ABI_MINOR 25
+#define SOF_ABI_MINOR 26
 #define SOF_ABI_PATCH 0
 
 /** \brief SOF ABI version number. Format within 32bit word is MMmmmppp */

src/platform/Kconfig

@@ -477,6 +477,17 @@ config CAVS_USE_LPRO_IN_WAITI
 	  After waiti exit clock source will be restored.
 	  Choose n if unclear.
 
+config L3_HEAP
+	bool "Use L3 memory heap"
+	default n
+	help
+	  Select this if L3 memory is supported on the platform and
+	  it is intended to be used for dynamic allocations.
+	  For Intel ACE platform the L3 memory is called
+	  IMR (Isolated Memory Region). Feature has been
+	  only tested on ACE platform.
+	  Choose n if unclear.
+
 config CAVS_IMR_D3_PERSISTENT
 	bool "Intel IMR content persistent on DSP in D3"
 	depends on CAVS && !CAVS_VERSION_1_5