This change unregisters KPB from async
notifications during kpb_free(). Additionally
reset main history buffer pointer.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This change moves history buffer allocation
from kpb_new() to kpb_prepare(). This is to
folow the calling convention with kernel.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch passes comp device pointer to buffering
and draining function as this pointer is needed to
finish reset requests.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch sets all LPSRAM related memory defines to
zero if CONFIG_LP_MEMORY_BANKS is not defined.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch changes the rules of LPSRAM enabling.
Now it is no longer platform dependent but rather
rely on config selection.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
To be able to use register read interfaces like shim_read()
we need to specify offset. This patch adds such offset for
LSPGCTL register.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch updates header file to support 24/32 bit samples
and also adds new default config.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
This patch adds an option to temporarily disable system
agent. This is especially needed when SOF is performing
long last tasks like draining.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
Component in comp_prepare() should change sink buffer
only when sink component is not connected to dma.
comp_set_sink_buffer() checks whether sink component
is not connected to dma and in that case it try to
resize sink buffer.
Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
Add dw dma buffer alignment in order to provide the
same buffer alignment as in the host side. Without
alignment it may appear mismatch between host and
dai buffer in simple pass-through pipeline (host->dai).
Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
This patch fixes the issue, where we've reenabled
the interrupts for the DSP, which sometimes caused
immediate DSP exception and overwrite of our dump.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Fixes the bug, where it tried to read epc1 value even,
if the pointer hasn't been previously set. It is only set
when there is an exception.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Moves panic related functions from arch/sof.h to newly created
arch/debug/panic.h. Also change definition of arch_dump_regs
function to take dump buffer from caller. It decreases the
number of included headers in arch/debug/panic.h.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Extends UserFrame in order to support full
context switch in the future, which will allow
to preempt tasks on the same irq level. Also this
patch adds additional 8-byte alignment fields to
automatically support coprocessors requirements.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Other global interrupt-related structs are already documented, add
missing documentation to struct irq_desc
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Instead of passing a pointer to the interrupt descriptor, embedded in
a cascading interrupt object and then using container_of() to get
back to the cascading interrupt, pass a pointer to it directly to
functions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When registering a cascading interrupt controller as a child of
another interrupt controller, no new child descriptor has to be
allocated, instead the embedded into the cascading interrupt
controller object descriptor has to be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently on cAVS platforms the two kinds of interrupts are treated
differently: the native DSP interrupts and "level" interrupts,
multiplexed by cascading interrupt controllers. For the latter
bitfields are used with both the parent DSP interrupt and the child
multiplexed interrupt numbers encoded in them. This is inflexible and
doesn't scale when more cascading interrupt controllers are added.
This patch switches over from using those bitfields to dynamically
mapping cascaded interrupts into a single plain interrupt number
space. Specifically this patch does the following:
- For interrupt conttrollers it adds an .irq_base field, which is the
base for child interrupts, multiplexed by this controller.
- An interrupt mapping function interrupt_get_irq() is added, which
uses the name of the cascading interrupt controller and an
interrupt number on that controller to create a logical interrupt
number.
- All uses of SOF_IRQ() and SOF_ID_IRQ() and related bitfield-
manipulation macros are removed.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When multiple interrupt handlers share the same interrupt, only
those, that enabled the interrupt on a specific CPU, have to be
called on that CPU.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The SPI driver only supports the DMA mode, its IRQ line isn't used
and the IRQ number in Sue Creek data is wrong. Remove the field
completely.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Use the platform provided IDC IRQ number only once and save the
number in a private field. This relies on the fact, that the
interrupt number is the same on all cores.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Use the platform provided scheduler IRQ number only once and save the
number in a private field.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Where available, use the IRQ number of the parent instead of
extracting it from the child's interrupt, using SOF_IRQ_NUMBER().
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
DSP interrupts have their own interrupt number in parent interrupt
bits, therefore using SOF_IRQ_NUMBER() for them is redundant.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The only two uses of SOF_IRQ_CPU() are currently in irq_mask() and
irq_unmask() on cAVS. However, those functions are always called
after interrupt_get_parent(), which makes sure, that the CPU, encoded
into the IRQ is the same as the current one. Therefore we can also
just use the current CPU in irq_mask() and irq_unmask().
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Most interrupts in SOF are handled completely locally: they are
registered, enabled, disabled, and handled on one and the same core.
There is only one case, where interrupts have to be unmasked on a
different core: in idc_enable_interrupts(). To make this possible
without using the CPU field in the IRQ bitfield we add a "cpu"
argument to interrupt_mask() and interrupt_unmask() functions.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add interrupt controller .mask() and .unmask() operations. Use them
instead of platform_interrupt_mask() and platform_interrupt_unmask().
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently cascading interrupt controller descriptors are registered
per core. This works well with Xtensa's "levelN" IRQ controllers
because their child interrupt lines can be masked per core. However
generic interrupt controllers do not have such a capability, which
makes registering them per core meaningless and error-prone. Switch
over to global IRQ descriptors, allocating them from non-cacheable
memory to avoid having to manually synchronise them at run-time.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Instead of checking one bit at a time, use ffs() to only handle set
bits in the interrupt status. Also fix the unhandled interrupt
detection logic: complain only if no handler has been found for a
given interrupt.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add a list of interrupt controllers, that will be allocated
at run-time from non-cacheable memory, and functions to perform such
a registration and to search through the list.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Until now cavs/interrupt.c used to call interrupt_get_parent() where
it had to verify whether an interrupt was a DSP interrupt or a
cascaded one. That function is rather heavy - it takes a spin-lock,
scans a list of all cascading interrupt controllers and checks their
interrupt numbers. Whereas that check can be performed much easier
and faster by simply checking the "level" field of the IRQ token.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
platform_interrupt_mask() and platform_interrupt_unmask() have a
"mask" parameter, that is actually never used. It is only used on
baytrail, but the only use of those functions on that platform is
from the ssp.c driver, where mask is fixed to 1. Besides the meaning
of that parameter was unclear: it would be logical to assume, that it
is a bitmask that has to be applied to a masking register, but often
those functions were called with mask=0, which makes no sense. This
patch removes that parameter.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Currently the SOF API in addition to interrupt_clear() and
interrupt_set() functions also has platform_interrupt_clear() and
platform_interrupt_set(). Those functions are partially overlapping
and their choice is confusing. Unify them to only use the former
variant - without the platform_ prefix.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Marcin Rajwa