OrgACRN
/
sof
mirror of https://github.com/thesofproject/sof.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

interrupt: remove an unused function parameter 

platform_interrupt_mask() and platform_interrupt_unmask() have a
"mask" parameter, that is actually never used. It is only used on
baytrail, but the only use of those functions on that platform is
from the ssp.c driver, where mask is fixed to 1. Besides the meaning
of that parameter was unclear: it would be logical to assume, that it
is a bitmask that has to be applied to a masking register, but often
those functions were called with mask=0, which makes no sense. This
patch removes that parameter.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2019-02-21 13:13:37 +01:00 committed by Liam Girdwood
parent 45f29f0bec
commit 9d4307fb5a
9 changed files with 35 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/xtensa/drivers/idc.c
View File

@ -52,7 +52,7 @@ void idc_enable_interrupts(int target_core, int source_core)
{
idc_write(IPC_IDCCTL, target_core,
IPC_IDCCTL_IDCTBIE(source_core));
platform_interrupt_unmask(PLATFORM_IDC_INTERRUPT(target_core), 0);
platform_interrupt_unmask(PLATFORM_IDC_INTERRUPT(target_core));
}
/**

4
src/drivers/imx/interrupt.c
View File

@ -30,5 +30,5 @@ uint32_t platform_interrupt_get_enabled(void)
return 0;
}
void platform_interrupt_mask(uint32_t irq, uint32_t mask) {}
void platform_interrupt_unmask(uint32_t irq, uint32_t mask) {}
void platform_interrupt_mask(uint32_t irq) {}
void platform_interrupt_unmask(uint32_t irq) {}

40
src/drivers/intel/baytrail/interrupt.c
View File

@ -84,36 +84,36 @@ uint32_t platform_interrupt_get_enabled(void)
return shim_read(SHIM_PIMR);
}
void platform_interrupt_mask(uint32_t irq, uint32_t mask)
void platform_interrupt_mask(uint32_t irq)
{
switch (irq) {
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_PIMR, mask << 3);
shim_write(SHIM_PIMR, 1 << 3);
break;
case IRQ_NUM_EXT_SSP1:
shim_write(SHIM_PIMR, mask << 4);
shim_write(SHIM_PIMR, 1 << 4);
break;
case IRQ_NUM_EXT_SSP2:
shim_write(SHIM_PIMR, mask << 5);
shim_write(SHIM_PIMR, 1 << 5);
break;
case IRQ_NUM_EXT_DMAC0:
shim_write(SHIM_PIMR, mask << 16);
shim_write(SHIM_PIMR, 1 << 16);
break;
case IRQ_NUM_EXT_DMAC1:
shim_write(SHIM_PIMR, mask << 24);
shim_write(SHIM_PIMR, 1 << 24);
break;
#if defined CONFIG_CHERRYTRAIL
case IRQ_NUM_EXT_DMAC2:
shim_write(SHIM_PIMRH, mask << 8);
shim_write(SHIM_PIMRH, 1 << 8);
break;
case IRQ_NUM_EXT_SSP3:
shim_write(SHIM_PIMRH, mask << 0);
shim_write(SHIM_PIMRH, 1 << 0);
break;
case IRQ_NUM_EXT_SSP4:
shim_write(SHIM_PIMRH, mask << 1);
shim_write(SHIM_PIMRH, 1 << 1);
break;
case IRQ_NUM_EXT_SSP5:
shim_write(SHIM_PIMRH, mask << 2);
shim_write(SHIM_PIMRH, 1 << 2);
break;
#endif
default:
@ -121,36 +121,36 @@ void platform_interrupt_mask(uint32_t irq, uint32_t mask)
}
}
void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
void platform_interrupt_unmask(uint32_t irq)
{
switch (irq) {
case IRQ_NUM_EXT_SSP0:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 3));
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 3));
break;
case IRQ_NUM_EXT_SSP1:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 4));
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 4));
break;
case IRQ_NUM_EXT_SSP2:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 5));
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 5));
break;
case IRQ_NUM_EXT_DMAC0:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 16));
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 16));
break;
case IRQ_NUM_EXT_DMAC1:
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(mask << 24));
shim_write(SHIM_PIMR, shim_read(SHIM_PIMR) & ~(1 << 24));
break;
#if defined CONFIG_CHERRYTRAIL
case IRQ_NUM_EXT_DMAC2:
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 8));
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(1 << 8));
break;
case IRQ_NUM_EXT_SSP3:
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 0));
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(1 << 0));
break;
case IRQ_NUM_EXT_SSP4:
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 1));
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(1 << 1));
break;
case IRQ_NUM_EXT_SSP5:
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(mask << 2));
shim_write(SHIM_PIMRH, shim_read(SHIM_PIMRH) & ~(1 << 2));
break;
#endif
default:

4
src/drivers/intel/cavs/dmic.c
View File

@ -1537,7 +1537,7 @@ static int dmic_probe(struct dai *dai)
/* Disable dynamic clock gating for dmic before touching any reg */
pm_runtime_get_sync(DMIC_CLK, dai->index);
platform_interrupt_unmask(dmic_irq(dai), 1);
platform_interrupt_unmask(dmic_irq(dai));
interrupt_enable(dmic_irq(dai));
return 0;
@ -1548,7 +1548,7 @@ static int dmic_remove(struct dai *dai)
int i;
interrupt_disable(dmic_irq(dai));
platform_interrupt_mask(dmic_irq(dai), 0);
platform_interrupt_mask(dmic_irq(dai));
interrupt_unregister(dmic_irq(dai), dai);
pm_runtime_put_sync(DMIC_CLK, dai->index);

4
src/drivers/intel/cavs/interrupt.c
View File

@ -164,7 +164,7 @@ uint32_t platform_interrupt_get_enabled(void)
return 0;
}
void platform_interrupt_mask(uint32_t irq, uint32_t mask)
void platform_interrupt_mask(uint32_t irq)
{
int core = SOF_IRQ_CPU(irq);
@ -187,7 +187,7 @@ void platform_interrupt_mask(uint32_t irq, uint32_t mask)
}
}
void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
void platform_interrupt_unmask(uint32_t irq)
{
int core = SOF_IRQ_CPU(irq);

4
src/drivers/intel/cavs/timer.c
View File

@ -170,7 +170,7 @@ void timer_enable(struct timer *timer)
interrupt_enable(timer->irq);
break;
case TIMER3:
platform_interrupt_unmask(timer->irq, 0);
platform_interrupt_unmask(timer->irq);
break;
}
}
@ -184,7 +184,7 @@ void timer_disable(struct timer *timer)
interrupt_disable(timer->irq);
break;
case TIMER3:
platform_interrupt_mask(timer->irq, 0);
platform_interrupt_mask(timer->irq);
break;
}
}

4
src/drivers/intel/haswell/interrupt.c
View File

@ -48,7 +48,7 @@ uint32_t platform_interrupt_get_enabled(void)
return shim_read(SHIM_IMRD);
}
void platform_interrupt_mask(uint32_t irq, uint32_t mask)
void platform_interrupt_mask(uint32_t irq)
{
switch (irq) {
case IRQ_NUM_EXT_SSP0:
@ -68,7 +68,7 @@ void platform_interrupt_mask(uint32_t irq, uint32_t mask)
}
}
void platform_interrupt_unmask(uint32_t irq, uint32_t mask)
void platform_interrupt_unmask(uint32_t irq)
{
switch (irq) {
case IRQ_NUM_EXT_SSP0:

4
src/drivers/interrupt.c
View File

@ -138,7 +138,7 @@ static uint32_t irq_enable_child(struct irq_desc *parent, int irq)
parent->enabled_count++;
/* enable the child interrupt */
platform_interrupt_unmask(irq, 0);
platform_interrupt_unmask(irq);
}
}
@ -165,7 +165,7 @@ static uint32_t irq_disable_child(struct irq_desc *parent, int irq)
parent->enabled_count--;
/* disable the child interrupt */
platform_interrupt_mask(irq, 0);
platform_interrupt_mask(irq);
}
}

4
src/include/sof/drivers/interrupt.h
View File

@ -66,8 +66,8 @@ struct irq_desc *platform_irq_get_parent(uint32_t irq);
void platform_interrupt_set(uint32_t irq);
void platform_interrupt_clear(uint32_t irq, uint32_t mask);
uint32_t platform_interrupt_get_enabled(void);
void platform_interrupt_mask(uint32_t irq, uint32_t mask);
void platform_interrupt_unmask(uint32_t irq, uint32_t mask);
void platform_interrupt_mask(uint32_t irq);
void platform_interrupt_unmask(uint32_t irq);
static inline void interrupt_set(int irq)
{