After commit f639fc8e88 ("copier: rename parent_dev to dev") FW for MTL
platform is not building. This should be detected as merge conflict but it
went unnoticed.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
After dai device was removed, there is no parent device
and dai device classification, only one device left for copier.
The input ipc config is exactly copier device config, no
need extra assignment.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
parent_dev previously used as copier device, and corresponding
child_dev is host and dai, after host and dai device remove,
there is no concept for parent_dev, rename it to dev.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
In ipc3 module creation, it is possible that ipc data
is invalid or corrupted, in this case, module init may crash.
This patch is adding error handling to avoid crash.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
This patch add synchronized FPI updates of HD-A gateways. Driver can
define group of such gateways via module init IPC. The driver may also
specify an update period for each group, different than the default one
determined by the system tick frequency.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch temporary extends comp_ipc_config struct by the value of
input configuration size. Each module receive its own configuration at
creation (MODULE_INIT IPC). In case of a gateway those configuration can
contain additional value (aux_conf). The only way to check if such
config was received is to compare size of the data received via ipc and
standard configuration size.
This solution is temporary because ultimately it would be necessary to
transfer to each module the size of the received configuration along
with a pointer to the configuration itself. Just like the test is in the
case of a module adapter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit changes implementation of DP scheduler
At start point an incorrect assumption has been taken
that it is enough to have one single instance of
DP scheduler located on a primary core
This commit introduces one DP instance per core
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
SAI can be configured for a one bclk wide frame sync pulse
by setting CR4 SYWD to 0. The REG_SAI_CR4_SYWD()
macro subtracts 1 from its argument which resulted in
bad things happening. So use 1 as correct macro argument.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
The imx SAI driver used hardcoded clock dividers, word lengths
and #ifdefs to deal with differences between SOCs. Changed it
to respect all the SAI_CONFIG parameters.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
Increase PLATFORM_MAX_CHANNELS and PLATFORM_MAX_STREAMS
to 8 in order to enable the use of certain
components (e.g. 'volume') with 8 channels.
This necessitates an increased HEAP_RUNTIME_SIZE.
Signed-off-by: Alexander Boehm <aboehm@eurofunk.com>
No need to check every 250uS for ipc completion, relax this to avoid
any busy scheduling.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
there is no usage for mixin and mixout ipc_config frame
format, remove it in its init function, frame_fmt will be
calculated and assigned in params accordingly, also most of other
modules init funciton does not have this conversion.
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
Add virtual heap allocators that allocate on proper heaps and
map physical memory where nesscessary.
Add free function that frees up the virtual heap memory and
unmaps physical memory when possible.
Virtual heap allocator allows using virtual memory as a base
for allocation and booking memory. Physical memory banks
will be mapped when needed allowing for greater flexibility
with mapping.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
In the case of DMA channels using the same IRQ line
the same interrupt handler with different data is
registered multiple times for the same interrupt.
This approach works perfectly fine when using the IRQ_STEER
IP since the way its driver works is it allows registering
multiple handlers+data for the same INTID.
When switching to ARM64, this approach no longer works since
the last irq_handler/irq_data pair will overwrite the previous
one for the same INTID. Because of this, the IRQ bit from the
DMA channel may not get cleared when multiple pipeline tasks
are scheduled. This reasoning applies to the ARM64 architecture
with GICv3 interrupt controller.
To overcome this, the Zephyr DMA domain now holds a list
of channels using the same IRQ. When the DMA IRQ gets triggered,
the handler will iterate through the list of channels using the
same IRQ and clear the interrupt.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This will allow to correctly set multiple pipelines state
even if they are allocated on different cores.
ipc4_set_pipeline_state will check if several cores are involved
- set ppl state if only current core requested
- process IPC on another core if only single secondary core requested
- send IDC messages if several secondary cores involved
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
According to MU's documentation from the i.MX TRM, setting
the GIRn bit to 1 if already 1 may lead to issuing a second interrupt.
This leads to kernel errors such as:
"reply size (16) exceeds the buffer size (12)"
because of the fact that the MU IRQ is triggered prematurely and
the firmware doesn't have enough time to write the reply. As such,
the host will read the message it has sent to the firmware instead
of its reply.
To fix this, make sure that GIRn is set to 0 before setting it 1.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
When using buffer_attach() on MediaTek platform after commit 3e3d0cde,
invalidating the dcache of a list can result in DSP panic.
To make sure that cached and uncached access is performed correctly on
Intel DSP implementations, invalidating the cache is necessary only for
INTEL platform. Therefore, adding #if CONFIG_INTEL to make the line
specific to INTEL platform.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Mark enums that are unused or never implemented as deprecated since they
will never be implemented as IPC3 is legacy.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Fix the comments of align_frame_cnt and align_shift_idx to
make them more clear and understandable.
Signed-off-by: Andrula Song <andrula.song@intel.com>
Pull in following rimage changes:
aa0ac9eae6 rimage.c: fix bug where -p requires a new
and ignored parameter
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
In last time copier code split, it split multi-endpoint copy and
module copy with commit: e424b87, source buffer consume was missed,
added it back with this PR.
Fixes:#7979
Signed-off-by: Baofeng Tian <baofeng.tian@intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Calling zephyr_ll_task_cancel() for a task which was actually never
scheduled results later in panic in zephyr_ll_task_done().
The fix makes zephyr_ll_task_cancel() do nothing for tasks which were
only initialized but never scheduled.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Commit 05871a16de ("pipeline2.0: add source/sink api to
audio_stream") added two new fields to `struct audio_stream`:
struct audio_stream {
+ struct sof_source source_api;
+ struct sof_sink sink_api;
and because `struct audio_stream` is part of `struct comp_buffer`
we see an increase of `struct comp_buffer` size from 256 to 384.
With this modification, i.MX mixer use case goes out of memory:
c0 dma-trace src/lib/alloc.c:765 ERROR failed to alloc 0x180 bytes zone 0x4 caps 0x1 flags 0x0
c0 dma-trace src/audio/buffer.c:51 ERROR buffer_alloc(): could not alloc structure
This is not ideal. Anyhow, it was necessary for new source/sink API.
Fix this by increasing the number of 512-byte heap blocks to 32.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Pipeline data is allocated in cached space. This workaround
prevents from accessing another core pipeline data when
calculating latency.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
To support pipelines connection between cores, ipc4_create_buffer()
must be able to create buffer shared between source and sink
components created on different cores. ipc4_create_buffer() requires
source component obs size. When both source and sink components
created on same core, ipc4_create_buffer() is executed on that core,
otherwise it is executed of core 0 (IPC processing core). So for the
case when source and sink components are created on different cores
comp_get_attribute_remote() is used to receive source obs size.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
bind/unbind handler must be called from core on which component was
created.
When both source and sink components are created on same core,
bind/unbind IPC is processed on that core. However, when connected
source and sink are on different cores, IPC is processed on core 0.
Hence comp_bind_remote() and comp_unbide_remote() is added to call
bind/unbide from proper core.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Utilize the posix build so that as many components as possible can be
built at once. Also build a bunch of `default n` components as well.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Add support to specify an overlay file to use with the fuzz script and
another flag to build without fuzzing
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Tomasz Leman