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2 Commits

Author SHA1 Message Date
Kai Vehmanen 0741e1eb00 boards: ace30: enable SOF log level at INF level 
Re-enable normal INFO level log output for ace30_ptl target.
Move the limited log level setting to FPGA overlay.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
 2024-09-05 16:22:40 +03:00
Jaroslaw Stelter 0f25a31089 ptl: Add FPGA overlay configuration 
Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
 2024-06-24 16:15:41 +02:00