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topology: sof-cnl-nocodec: prepare for different multicore configurations 

Not all devices have 4 cores, some only have 2 and even APL/GLK is
currently limited to a single core.

For now we still use a single core for all topologies, we will enable
multi-core in a follow-up patch.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
Pierre-Louis Bossart 2021-06-18 15:39:41 -05:00
parent 4050ff6c31
commit fdd8ec03b5
1 changed files with 35 additions and 2 deletions
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37
tools/topology/topology1/sof-cnl-nocodec.m4
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@ -17,6 +17,16 @@ include(`sof/tokens.m4')
# Include DSP configuration
include(`platform/intel/'PLATFORM`.m4')
# bxt has 2 cores but currently only one is enabled in the build
ifelse(PLATFORM, `bxt', `define(NCORES, 1)')
ifelse(PLATFORM, `cnl', `define(NCORES, 4)')
ifelse(PLATFORM, `cml', `define(NCORES, 4)')
ifelse(PLATFORM, `icl', `define(NCORES, 4)')
ifelse(PLATFORM, `jsl', `define(NCORES, 2)')
ifelse(PLATFORM, `tgl', `define(NCORES, 4)')
ifelse(PLATFORM, `ehl', `define(NCORES, 4)')
ifelse(PLATFORM, `adl', `define(NCORES, 4)')
define(CHANNELS, `4')
define(DMIC_PCM_48k_ID, `10')
@ -37,11 +47,34 @@ define(DMIC16KPROC, `eq-iir-volume')
define(DMICPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_48khz.m4')
define(DMIC16KPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_16khz.m4')
include(`platform/intel/intel-generic-dmic.m4')
ifelse(NCORES, `4',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')
ifelse(NCORES, `2',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')
ifelse(NCORES, `1',
`
define(DMIC_48k_CORE_ID, `0')
define(DMIC_16k_CORE_ID, `0')
define(SSP0_CORE_ID, `0')
define(SSP1_CORE_ID, `0')
define(SSP2_CORE_ID, `0')
')
include(`platform/intel/intel-generic-dmic.m4')
ifelse(PLATFORM, `bxt',
`