From fdd8ec03b56c104eb7d739a3a4ad8d3fe5b7f773 Mon Sep 17 00:00:00 2001 From: Pierre-Louis Bossart Date: Fri, 18 Jun 2021 15:39:41 -0500 Subject: [PATCH] topology: sof-cnl-nocodec: prepare for different multicore configurations Not all devices have 4 cores, some only have 2 and even APL/GLK is currently limited to a single core. For now we still use a single core for all topologies, we will enable multi-core in a follow-up patch. Signed-off-by: Pierre-Louis Bossart --- tools/topology/topology1/sof-cnl-nocodec.m4 | 37 +++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/tools/topology/topology1/sof-cnl-nocodec.m4 b/tools/topology/topology1/sof-cnl-nocodec.m4 index da140c437..c086cdabb 100644 --- a/tools/topology/topology1/sof-cnl-nocodec.m4 +++ b/tools/topology/topology1/sof-cnl-nocodec.m4 @@ -17,6 +17,16 @@ include(`sof/tokens.m4') # Include DSP configuration include(`platform/intel/'PLATFORM`.m4') +# bxt has 2 cores but currently only one is enabled in the build +ifelse(PLATFORM, `bxt', `define(NCORES, 1)') +ifelse(PLATFORM, `cnl', `define(NCORES, 4)') +ifelse(PLATFORM, `cml', `define(NCORES, 4)') +ifelse(PLATFORM, `icl', `define(NCORES, 4)') +ifelse(PLATFORM, `jsl', `define(NCORES, 2)') +ifelse(PLATFORM, `tgl', `define(NCORES, 4)') +ifelse(PLATFORM, `ehl', `define(NCORES, 4)') +ifelse(PLATFORM, `adl', `define(NCORES, 4)') + define(CHANNELS, `4') define(DMIC_PCM_48k_ID, `10') @@ -37,11 +47,34 @@ define(DMIC16KPROC, `eq-iir-volume') define(DMICPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_48khz.m4') define(DMIC16KPROC_FILTER1, `eq_iir_coef_highpass_40hz_20db_16khz.m4') -include(`platform/intel/intel-generic-dmic.m4') - +ifelse(NCORES, `4', +` +define(DMIC_48k_CORE_ID, `0') +define(DMIC_16k_CORE_ID, `0') define(SSP0_CORE_ID, `0') define(SSP1_CORE_ID, `0') define(SSP2_CORE_ID, `0') +') + +ifelse(NCORES, `2', +` +define(DMIC_48k_CORE_ID, `0') +define(DMIC_16k_CORE_ID, `0') +define(SSP0_CORE_ID, `0') +define(SSP1_CORE_ID, `0') +define(SSP2_CORE_ID, `0') +') + +ifelse(NCORES, `1', +` +define(DMIC_48k_CORE_ID, `0') +define(DMIC_16k_CORE_ID, `0') +define(SSP0_CORE_ID, `0') +define(SSP1_CORE_ID, `0') +define(SSP2_CORE_ID, `0') +') + +include(`platform/intel/intel-generic-dmic.m4') ifelse(PLATFORM, `bxt', `