mirror of https://github.com/thesofproject/sof.git
tgl: enable WOVCRO clock
This will allow to save significant amount of SOC power in low power S0ix WoV Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
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908838ac15
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@ -305,18 +305,32 @@ static int clock_platform_set_cpu_freq(int clock, int freq_idx)
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void platform_clock_init(struct sof *sof)
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{
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uint32_t platform_lowest_clock = CPU_LOWEST_FREQ_IDX;
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int i;
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sof->clocks =
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cache_to_uncache((struct clock_info *)platform_clocks_info);
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#if CAVS_VERSION == CAVS_VERSION_2_5
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/*
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* Check HW version clock capabilities
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* Try to request WOV_CRO clock, if it fails use LPRO clock
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*/
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shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_WOV_CRO_REQUEST);
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if (shim_read(SHIM_CLKCTL) & SHIM_CLKCTL_WOV_CRO_REQUEST)
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shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) & ~SHIM_CLKCTL_WOV_CRO_REQUEST);
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else
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platform_lowest_clock = CPU_LPRO_FREQ_IDX;
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#endif
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for (i = 0; i < CONFIG_CORE_COUNT; i++) {
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sof->clocks[i] = (struct clock_info) {
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.freqs_num = NUM_CPU_FREQ,
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.freqs = cpu_freq,
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.default_freq_idx = CPU_DEFAULT_IDX,
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.current_freq_idx = CPU_DEFAULT_IDX,
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.lowest_freq_idx = CPU_LOWEST_FREQ_IDX,
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.lowest_freq_idx = platform_lowest_clock,
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.notification_id = NOTIFIER_ID_CPU_FREQ,
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.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
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.set_freq = clock_platform_set_cpu_freq,
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@ -16,11 +16,13 @@
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#define CLK_MAX_CPU_HZ 400000000
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#define CPU_LPRO_FREQ_IDX 0
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#define CPU_WOVCRO_FREQ_IDX 0
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#define CPU_HPRO_FREQ_IDX 1
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#define CPU_LPRO_FREQ_IDX 1
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#define CPU_LOWEST_FREQ_IDX CPU_LPRO_FREQ_IDX
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#define CPU_HPRO_FREQ_IDX 2
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#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX
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#if CONFIG_CAVS_LPRO_ONLY
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#define CPU_DEFAULT_IDX CPU_LPRO_FREQ_IDX
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@ -30,7 +32,7 @@
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#define SSP_DEFAULT_IDX 1
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#define NUM_CPU_FREQ 2
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#define NUM_CPU_FREQ 3
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#define NUM_SSP_FREQ 3
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@ -113,6 +113,9 @@
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/** \brief Request HP RING Oscillator Clock */
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#define SHIM_CLKCTL_RHROSCC BIT(31)
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/** \brief Request WOVCRO Clock */
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#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4)
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/** \brief Request XTAL Oscillator Clock */
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#define SHIM_CLKCTL_RXOSCC BIT(30)
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@ -130,6 +133,7 @@
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/** \brief Oscillator Clock Select*/
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#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
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#define SHIM_CLKCTL_OCS_LP_RING 0
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#define SHIM_CLKCTL_WOVCROSC BIT(3)
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/** \brief LP Memory Clock Select */
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#define SHIM_CLKCTL_LMCS_DIV2 0
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@ -172,6 +176,9 @@
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/** \brief HP RING Oscillator Clock Status */
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#define SHIM_CLKSTS_HROSCCS BIT(31)
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/** \brief WOVCRO Clock Status */
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#define SHIM_CLKSTS_WOV_CRO BIT(4)
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/** \brief XTAL Oscillator Clock Status */
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#define SHIM_CLKSTS_XOSCCS BIT(30)
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@ -10,11 +10,14 @@
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#include <sof/lib/clk.h>
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const struct freq_table platform_cpu_freq[] = {
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{ 38400000, 38400 },
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{ 120000000, 120000 },
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{ CLK_MAX_CPU_HZ, 400000 },
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};
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const uint32_t cpu_freq_enc[] = {
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SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST |
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SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
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SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING |
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SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
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SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING |
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@ -22,8 +25,9 @@ const uint32_t cpu_freq_enc[] = {
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};
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const uint32_t cpu_freq_status_mask[] = {
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SHIM_CLKSTS_WOV_CRO,
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SHIM_CLKSTS_LROSCCS,
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SHIM_CLKSTS_HROSCCS,
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SHIM_CLKSTS_HROSCCS
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};
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STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq),
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