From fadd8e7077df1d09c94288747c0d6c9bb9b31775 Mon Sep 17 00:00:00 2001
From: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
Date: Mon, 7 Sep 2020 18:20:09 +0200
Subject: [PATCH] tgl: enable WOVCRO clock

This will allow to save significant amount of SOC power
in low power S0ix WoV

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
---
 src/platform/intel/cavs/lib/clk.c                | 16 +++++++++++++++-
 .../tigerlake/include/platform/lib/clk.h         | 10 ++++++----
 .../tigerlake/include/platform/lib/shim.h        |  7 +++++++
 src/platform/tigerlake/lib/clk.c                 |  6 +++++-
 4 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/src/platform/intel/cavs/lib/clk.c b/src/platform/intel/cavs/lib/clk.c
index a0057c220..7ab3e337f 100644
--- a/src/platform/intel/cavs/lib/clk.c
+++ b/src/platform/intel/cavs/lib/clk.c
@@ -305,18 +305,32 @@ static int clock_platform_set_cpu_freq(int clock, int freq_idx)
 
 void platform_clock_init(struct sof *sof)
 {
+	uint32_t platform_lowest_clock = CPU_LOWEST_FREQ_IDX;
 	int i;
 
 	sof->clocks =
 		cache_to_uncache((struct clock_info *)platform_clocks_info);
 
+#if CAVS_VERSION == CAVS_VERSION_2_5
+	/*
+	 * Check HW version clock capabilities
+	 * Try to request WOV_CRO clock, if it fails use LPRO clock
+	 */
+
+	shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_WOV_CRO_REQUEST);
+	if (shim_read(SHIM_CLKCTL) & SHIM_CLKCTL_WOV_CRO_REQUEST)
+		shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) & ~SHIM_CLKCTL_WOV_CRO_REQUEST);
+	else
+		platform_lowest_clock = CPU_LPRO_FREQ_IDX;
+#endif
+
 	for (i = 0; i < CONFIG_CORE_COUNT; i++) {
 		sof->clocks[i] = (struct clock_info) {
 			.freqs_num = NUM_CPU_FREQ,
 			.freqs = cpu_freq,
 			.default_freq_idx = CPU_DEFAULT_IDX,
 			.current_freq_idx = CPU_DEFAULT_IDX,
-			.lowest_freq_idx = CPU_LOWEST_FREQ_IDX,
+			.lowest_freq_idx = platform_lowest_clock,
 			.notification_id = NOTIFIER_ID_CPU_FREQ,
 			.notification_mask = NOTIFIER_TARGET_CORE_MASK(i),
 			.set_freq = clock_platform_set_cpu_freq,
diff --git a/src/platform/tigerlake/include/platform/lib/clk.h b/src/platform/tigerlake/include/platform/lib/clk.h
index fe857fe95..dae76a9c5 100644
--- a/src/platform/tigerlake/include/platform/lib/clk.h
+++ b/src/platform/tigerlake/include/platform/lib/clk.h
@@ -16,11 +16,13 @@
 
 #define CLK_MAX_CPU_HZ	400000000
 
-#define CPU_LPRO_FREQ_IDX 0
+#define CPU_WOVCRO_FREQ_IDX 0
 
-#define CPU_HPRO_FREQ_IDX 1
+#define CPU_LPRO_FREQ_IDX 1
 
-#define CPU_LOWEST_FREQ_IDX CPU_LPRO_FREQ_IDX
+#define CPU_HPRO_FREQ_IDX 2
+
+#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX
 
 #if CONFIG_CAVS_LPRO_ONLY
 #define CPU_DEFAULT_IDX CPU_LPRO_FREQ_IDX
@@ -30,7 +32,7 @@
 
 #define SSP_DEFAULT_IDX	1
 
-#define NUM_CPU_FREQ	2
+#define NUM_CPU_FREQ	3
 
 #define NUM_SSP_FREQ	3
 
diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h
index 38d6de84c..2a1edbb75 100644
--- a/src/platform/tigerlake/include/platform/lib/shim.h
+++ b/src/platform/tigerlake/include/platform/lib/shim.h
@@ -113,6 +113,9 @@
 /** \brief Request HP RING Oscillator Clock */
 #define SHIM_CLKCTL_RHROSCC	BIT(31)
 
+/** \brief Request WOVCRO Clock */
+#define SHIM_CLKCTL_WOV_CRO_REQUEST	BIT(4)
+
 /** \brief Request XTAL Oscillator Clock */
 #define SHIM_CLKCTL_RXOSCC	BIT(30)
 
@@ -130,6 +133,7 @@
 /** \brief Oscillator Clock Select*/
 #define SHIM_CLKCTL_OCS_HP_RING		BIT(2)
 #define SHIM_CLKCTL_OCS_LP_RING		0
+#define SHIM_CLKCTL_WOVCROSC		BIT(3)
 
 /** \brief LP Memory Clock Select */
 #define SHIM_CLKCTL_LMCS_DIV2	0
@@ -172,6 +176,9 @@
 /** \brief HP RING Oscillator Clock Status */
 #define SHIM_CLKSTS_HROSCCS	BIT(31)
 
+/** \brief WOVCRO Clock Status */
+#define SHIM_CLKSTS_WOV_CRO	BIT(4)
+
 /** \brief XTAL Oscillator Clock Status */
 #define SHIM_CLKSTS_XOSCCS	BIT(30)
 
diff --git a/src/platform/tigerlake/lib/clk.c b/src/platform/tigerlake/lib/clk.c
index 276fded13..16288695f 100644
--- a/src/platform/tigerlake/lib/clk.c
+++ b/src/platform/tigerlake/lib/clk.c
@@ -10,11 +10,14 @@
 #include <sof/lib/clk.h>
 
 const struct freq_table platform_cpu_freq[] = {
+	{ 38400000, 38400 },
 	{ 120000000, 120000 },
 	{ CLK_MAX_CPU_HZ, 400000 },
 };
 
 const uint32_t cpu_freq_enc[] = {
+	SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST |
+		SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
 	SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING |
 		SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4,
 	SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING |
@@ -22,8 +25,9 @@ const uint32_t cpu_freq_enc[] = {
 };
 
 const uint32_t cpu_freq_status_mask[] = {
+	SHIM_CLKSTS_WOV_CRO,
 	SHIM_CLKSTS_LROSCCS,
-	SHIM_CLKSTS_HROSCCS,
+	SHIM_CLKSTS_HROSCCS
 };
 
 STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq),