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Merge pull request #11 from tlauda/issue-6 

cavs: platform: clear memory windows
This commit is contained in:
Liam Girdwood 2018-06-22 13:56:29 +01:00 committed by GitHub
parent 8a48cc4902 c79146e05e
commit fab2f4e782
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 20 additions and 0 deletions
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10
src/platform/apollolake/platform.c
View File

@ -167,21 +167,31 @@ static void platform_memory_windows_init(void)
io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
/* window1, for inbox/downlink mbox */
io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
| DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
/* window2, for debug */
io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
/* window3, for trace */
io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
}
int platform_init(struct sof *sof)

10
src/platform/cannonlake/platform.c
View File

@ -166,21 +166,31 @@ static void platform_memory_windows_init(void)
io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
/* window1, for inbox/downlink mbox */
io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
| DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
/* window2, for debug */
io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
/* window3, for trace */
io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
}
/* init HW */