From c79146e05ed0954a5f3763cd717e9c19cc025791 Mon Sep 17 00:00:00 2001 From: Tomasz Lauda Date: Fri, 22 Jun 2018 14:17:25 +0200 Subject: [PATCH] cavs: platform: clear memory windows Clear memory windows after initialization on APL and CNL. They were recently moved to the beginning of HPSRAM and since that area is also used by ROM, there was some unneeded data left. Signed-off-by: Tomasz Lauda --- src/platform/apollolake/platform.c | 10 ++++++++++ src/platform/cannonlake/platform.c | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/platform/apollolake/platform.c b/src/platform/apollolake/platform.c index a523b46ad..684cc74ec 100644 --- a/src/platform/apollolake/platform.c +++ b/src/platform/apollolake/platform.c @@ -167,21 +167,31 @@ static void platform_memory_windows_init(void) io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7); io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), + HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); + dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), + HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); /* window1, for inbox/downlink mbox */ io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7); io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE); /* window2, for debug */ io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7); io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE); /* window3, for trace */ io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7); io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); } int platform_init(struct sof *sof) diff --git a/src/platform/cannonlake/platform.c b/src/platform/cannonlake/platform.c index 54c146cac..6e5a020e4 100644 --- a/src/platform/cannonlake/platform.c +++ b/src/platform/cannonlake/platform.c @@ -166,21 +166,31 @@ static void platform_memory_windows_init(void) io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7); io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), + HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); + dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), + HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END); /* window1, for inbox/downlink mbox */ io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7); io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE); /* window2, for debug */ io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7); io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE); /* window3, for trace */ io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7); io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE); + bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); + dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE); } /* init HW */