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shim: cleanup and extend GPDMA shim registers 

Cleanups definitions of GPDMA shim registers for all cAVS platforms
and extends them by adding support for channel linear link position
control register.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda 2019-11-19 13:37:26 +01:00 committed by Liam Girdwood
parent 714859d925
commit d343039093
6 changed files with 56 additions and 12 deletions
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9
src/platform/apollolake/include/platform/lib/shim.h
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@ -201,6 +201,15 @@
#define SHIM_SPSREQ_RVNNP (0x1 << 0)
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0xC00
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80)
/** \brief GPDMA Channel Linear Link Position Control */
#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10)
#define SHIM_GPDMA_CHLLPC_EN BIT(5)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x)
/** \brief LDO Control */
#define SHIM_LDOCTL 0xA4
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)

7
src/platform/cannonlake/include/platform/lib/shim.h
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@ -163,12 +163,17 @@
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
/** \brief GPDMA Channel Linear Link Position Control */
#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

16
src/platform/icelake/include/platform/lib/shim.h
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@ -125,7 +125,6 @@
#define SHIM_LPSCTL_BATTR_0 BIT(12)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
/* Core clock PLL divisor */
@ -143,8 +142,19 @@
/* HP memory clock PLL divisor */
#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
#define GPDMA_CLKCTL(x) (0x78404 + x*0x100)
#define GPDMA_FDCGB (0x1 << 0)
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
/** \brief GPDMA Channel Linear Link Position Control */
#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

4
src/platform/intel/cavs/platform.c
View File

@ -420,8 +420,8 @@ int platform_init(struct sof *sof)
SHIM_CLKCTL_TCPLCG(0));
/* prevent LP GPDMA 0&1 clock gating */
io_reg_write(GPDMA_CLKCTL(0), GPDMA_FDCGB);
io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
shim_write(SHIM_GPDMA_CLKCTL(0), SHIM_CLKCTL_LPGPDMAFDCGB);
shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
/* prevent DSP Common power gating */
pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);

16
src/platform/suecreek/include/platform/lib/shim.h
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@ -125,7 +125,6 @@
#define SHIM_LPSCTL_BATTR_0 BIT(12)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
/* Core clock PLL divisor */
@ -143,8 +142,19 @@
/* HP memory clock PLL divisor */
#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
#define GPDMA_CLKCTL(x) (0x78404 + x*0x100)
#define GPDMA_FDCGB (0x1 << 0)
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
/** \brief GPDMA Channel Linear Link Position Control */
#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

16
src/platform/tigerlake/include/platform/lib/shim.h
View File

@ -125,7 +125,6 @@
#define SHIM_LPSCTL_BATTR_0 BIT(12)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x))
#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x))
/* Core clock PLL divisor */
@ -143,8 +142,19 @@
/* HP memory clock PLL divisor */
#define SHIM_CLKCTL_HPMPCS (0x1 << 0)
#define GPDMA_CLKCTL(x) (0x78404 + x*0x100)
#define GPDMA_FDCGB (0x1 << 0)
/** \brief GPDMA shim registers Control */
#define SHIM_GPDMA_BASE_OFFSET 0x6500
#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
/** \brief GPDMA Clock Control */
#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
/** \brief GPDMA Channel Linear Link Position Control */
#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
/* I2S SHIM Registers */
#define I2SLCTL 0x71C04