diff --git a/src/platform/apollolake/include/platform/lib/shim.h b/src/platform/apollolake/include/platform/lib/shim.h
index 06b82b5d2..35be91def 100644
--- a/src/platform/apollolake/include/platform/lib/shim.h
+++ b/src/platform/apollolake/include/platform/lib/shim.h
@@ -201,6 +201,15 @@
 
 #define SHIM_SPSREQ_RVNNP	(0x1 << 0)
 
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET	0xC00
+#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x80)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y)		(SHIM_GPDMA_BASE(x) + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN		BIT(5)
+#define SHIM_GPDMA_CHLLPC_DHRS(x)	SET_BITS(4, 0, x)
+
 /** \brief LDO Control */
 #define SHIM_LDOCTL		0xA4
 #define SHIM_LDOCTL_HPSRAM_MASK	(3 << 0)
diff --git a/src/platform/cannonlake/include/platform/lib/shim.h b/src/platform/cannonlake/include/platform/lib/shim.h
index a7b5ceb32..7e56d594c 100644
--- a/src/platform/cannonlake/include/platform/lib/shim.h
+++ b/src/platform/cannonlake/include/platform/lib/shim.h
@@ -163,12 +163,17 @@
 /** \brief GPDMA shim registers Control */
 #define SHIM_GPDMA_BASE_OFFSET	0x6500
 #define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
 /** \brief GPDMA Clock Control */
 #define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
-
 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
 #define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
 
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y)		(SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN		BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x)	SET_BITS(6, 0, x)
+
 #define L2LMCAP			0x71D00
 #define L2MPAT			0x71D04
 
diff --git a/src/platform/icelake/include/platform/lib/shim.h b/src/platform/icelake/include/platform/lib/shim.h
index b4f9e0328..3137c61db 100644
--- a/src/platform/icelake/include/platform/lib/shim.h
+++ b/src/platform/icelake/include/platform/lib/shim.h
@@ -125,7 +125,6 @@
 #define SHIM_LPSCTL_BATTR_0	BIT(12)
 
 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB(x)	(0x1 << (26 + x))
 #define SHIM_CLKCTL_TCPLCG(x)		(0x1 << (16 + x))
 
 /* Core clock PLL divisor */
@@ -143,8 +142,19 @@
 /* HP memory clock PLL divisor */
 #define SHIM_CLKCTL_HPMPCS	(0x1 << 0)
 
-#define GPDMA_CLKCTL(x)		(0x78404 + x*0x100)
-#define GPDMA_FDCGB		(0x1 << 0)
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET	0x6500
+#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y)		(SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN		BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x)	SET_BITS(6, 0, x)
 
 #define L2LMCAP			0x71D00
 #define L2MPAT			0x71D04
diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c
index 1fb05cee8..f5444218b 100644
--- a/src/platform/intel/cavs/platform.c
+++ b/src/platform/intel/cavs/platform.c
@@ -420,8 +420,8 @@ int platform_init(struct sof *sof)
 		SHIM_CLKCTL_TCPLCG(0));
 
 	/* prevent LP GPDMA 0&1 clock gating */
-	io_reg_write(GPDMA_CLKCTL(0), GPDMA_FDCGB);
-	io_reg_write(GPDMA_CLKCTL(1), GPDMA_FDCGB);
+	shim_write(SHIM_GPDMA_CLKCTL(0), SHIM_CLKCTL_LPGPDMAFDCGB);
+	shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
 
 	/* prevent DSP Common power gating */
 	pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_MASTER_CORE_ID);
diff --git a/src/platform/suecreek/include/platform/lib/shim.h b/src/platform/suecreek/include/platform/lib/shim.h
index 7c2434c6b..9fe736592 100644
--- a/src/platform/suecreek/include/platform/lib/shim.h
+++ b/src/platform/suecreek/include/platform/lib/shim.h
@@ -125,7 +125,6 @@
 #define SHIM_LPSCTL_BATTR_0	BIT(12)
 
 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB(x)	(0x1 << (26 + x))
 #define SHIM_CLKCTL_TCPLCG(x)		(0x1 << (16 + x))
 
 /* Core clock PLL divisor */
@@ -143,8 +142,19 @@
 /* HP memory clock PLL divisor */
 #define SHIM_CLKCTL_HPMPCS	(0x1 << 0)
 
-#define GPDMA_CLKCTL(x)		(0x78404 + x*0x100)
-#define GPDMA_FDCGB		(0x1 << 0)
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET	0x6500
+#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y)		(SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN		BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x)	SET_BITS(6, 0, x)
 
 #define L2LMCAP			0x71D00
 #define L2MPAT			0x71D04
diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h
index 8826cc9be..69a0720dc 100644
--- a/src/platform/tigerlake/include/platform/lib/shim.h
+++ b/src/platform/tigerlake/include/platform/lib/shim.h
@@ -125,7 +125,6 @@
 #define SHIM_LPSCTL_BATTR_0	BIT(12)
 
 /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
-#define SHIM_CLKCTL_LPGPDMAFDCGB(x)	(0x1 << (26 + x))
 #define SHIM_CLKCTL_TCPLCG(x)		(0x1 << (16 + x))
 
 /* Core clock PLL divisor */
@@ -143,8 +142,19 @@
 /* HP memory clock PLL divisor */
 #define SHIM_CLKCTL_HPMPCS	(0x1 << 0)
 
-#define GPDMA_CLKCTL(x)		(0x78404 + x*0x100)
-#define GPDMA_FDCGB		(0x1 << 0)
+/** \brief GPDMA shim registers Control */
+#define SHIM_GPDMA_BASE_OFFSET	0x6500
+#define SHIM_GPDMA_BASE(x)	(SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
+
+/** \brief GPDMA Clock Control */
+#define SHIM_GPDMA_CLKCTL(x)	(SHIM_GPDMA_BASE(x) + 0x4)
+/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
+#define SHIM_CLKCTL_LPGPDMAFDCGB	BIT(0)
+
+/** \brief GPDMA Channel Linear Link Position Control */
+#define SHIM_GPDMA_CHLLPC(x, y)		(SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
+#define SHIM_GPDMA_CHLLPC_EN		BIT(7)
+#define SHIM_GPDMA_CHLLPC_DHRS(x)	SET_BITS(6, 0, x)
 
 /* I2S SHIM Registers */
 #define I2SLCTL			0x71C04