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Merge pull request #480 from tlauda/topic/ssp-pm-fix 

pm_runtime: fix clock gating for SSP 4 & 5
This commit is contained in:
Liam Girdwood 2018-10-11 12:11:31 +01:00 committed by GitHub
parent 12ecadcfcc 30e7613e86
commit cc3fb1e4b3
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
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4
src/platform/intel/cavs/pm_runtime.c
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@ -76,7 +76,7 @@ static inline void cavs_pm_runtime_dis_ssp_clk_gating(uint32_t index)
shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
(index < DAI_NUM_SSP_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index)));
SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)));
trace_event(TRACE_CLASS_POWER,
"dis-ssp-clk-gating index %d CLKCTL %08x",
@ -90,7 +90,7 @@ static inline void cavs_pm_runtime_en_ssp_clk_gating(uint32_t index)
shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) &
~(index < DAI_NUM_SSP_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index)));
SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)));
trace_event(TRACE_CLASS_POWER,
"en-ssp-clk-gating index %d CLKCTL %08x",