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pm_runtime: fix clock gating for SSP 4 & 5 

Fixes clock gating switching for SSP 4 and 5.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda 2018-10-11 11:56:22 +02:00
parent 7996f1ac10
commit 30e7613e86
1 changed files with 2 additions and 2 deletions
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4
src/platform/intel/cavs/pm_runtime.c
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@ -76,7 +76,7 @@ static inline void cavs_pm_runtime_dis_ssp_clk_gating(uint32_t index)
shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) |
(index < DAI_NUM_SSP_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index)));
SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)));
trace_event(TRACE_CLASS_POWER,
"dis-ssp-clk-gating index %d CLKCTL %08x",
@ -90,7 +90,7 @@ static inline void cavs_pm_runtime_en_ssp_clk_gating(uint32_t index)
shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) &
~(index < DAI_NUM_SSP_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index)));
SHIM_CLKCTL_I2SEFDCGB(index - DAI_NUM_SSP_BASE)));
trace_event(TRACE_CLASS_POWER,
"en-ssp-clk-gating index %d CLKCTL %08x",