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ipc4: read linear link position for host driver. 

Linear link position is updated in llp register by GP-DMA
hardware. Now it is enabled by SOF FW but not used.

This patch set up a path to read it and update it to host
driver.

Signed-off-by: Rander Wang <rander.wang@intel.com>
This commit is contained in:
Rander Wang 2021-11-16 09:14:06 +08:00 committed by Liam Girdwood
parent 9a6569d48c
commit c2974bcb75
8 changed files with 39 additions and 0 deletions
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3
src/platform/apollolake/include/platform/lib/shim.h
View File

@ -209,6 +209,9 @@
#define SHIM_GPDMA_CHLLPC_EN BIT(5)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x)
#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
/** \brief LDO Control */
#define SHIM_LDOCTL 0xA4
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)

4
src/platform/baytrail/include/platform/drivers/dw-dma.h
View File

@ -62,6 +62,10 @@ static inline void platform_dw_dma_llp_enable(struct dma *dma,
static inline void platform_dw_dma_llp_disable(struct dma *dma,
struct dma_chan_data *chan) { }
static inline void platform_dw_dma_llp_read(struct dma *dma,
struct dma_chan_data *chan,
uint32_t *llp_l,
uint32_t *llp_u) { }
#endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */
#else

3
src/platform/cannonlake/include/platform/lib/shim.h
View File

@ -211,6 +211,9 @@
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

5
src/platform/haswell/include/platform/drivers/dw-dma.h
View File

@ -60,6 +60,11 @@ static inline void platform_dw_dma_llp_enable(struct dma *dma,
static inline void platform_dw_dma_llp_disable(struct dma *dma,
struct dma_chan_data *chan) { }
static inline void platform_dw_dma_llp_read(struct dma *dma,
struct dma_chan_data *chan,
uint32_t *llp_l,
uint32_t *llp_u) { }
#endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */
#else

3
src/platform/icelake/include/platform/lib/shim.h
View File

@ -205,6 +205,9 @@
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

15
src/platform/intel/cavs/include/cavs/drivers/dw-dma.h
View File

@ -58,6 +58,12 @@
#define DW_CHLLPC(dma, chan) \
SHIM_GPDMA_CHLLPC((dma)->plat_data.id, (chan)->index)
#define DW_CHLLPL(dma, chan) \
SHIM_GPDMA_CHLLPL((dma)->plat_data.id, (chan)->index)
#define DW_CHLLPU(dma, chan) \
SHIM_GPDMA_CHLLPU((dma)->plat_data.id, (chan)->index)
#define platform_dw_dma_set_class(chan, lli, class) \
(lli->ctrl_hi |= DW_CTLH_CLASS(class))
@ -85,6 +91,15 @@ static inline void platform_dw_dma_llp_disable(struct dma *dma,
shim_read(DW_CHLLPC(dma, chan)) & ~SHIM_GPDMA_CHLLPC_EN);
}
static inline void platform_dw_dma_llp_read(struct dma *dma,
struct dma_chan_data *chan,
uint32_t *llp_l,
uint32_t *llp_u)
{
*llp_l = shim_read(DW_CHLLPL(dma, chan));
*llp_u = shim_read(DW_CHLLPU(dma, chan));
}
static inline struct dw_lli *platform_dw_dma_lli_get(struct dw_lli *lli)
{
return cache_to_uncache(lli);

3
src/platform/suecreek/include/platform/lib/shim.h
View File

@ -200,6 +200,9 @@
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
#define L2LMCAP 0x71D00
#define L2MPAT 0x71D04

3
src/platform/tigerlake/include/platform/lib/shim.h
View File

@ -212,6 +212,9 @@
#define SHIM_GPDMA_CHLLPC_EN BIT(7)
#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
/* I2S SHIM Registers */
#define I2SLCTL 0x71C04