From c2974bcb75d34bdef09904991b9f01e5cd715494 Mon Sep 17 00:00:00 2001 From: Rander Wang Date: Tue, 16 Nov 2021 09:14:06 +0800 Subject: [PATCH] ipc4: read linear link position for host driver. Linear link position is updated in llp register by GP-DMA hardware. Now it is enabled by SOF FW but not used. This patch set up a path to read it and update it to host driver. Signed-off-by: Rander Wang --- .../apollolake/include/platform/lib/shim.h | 3 +++ .../baytrail/include/platform/drivers/dw-dma.h | 4 ++++ .../cannonlake/include/platform/lib/shim.h | 3 +++ .../haswell/include/platform/drivers/dw-dma.h | 5 +++++ src/platform/icelake/include/platform/lib/shim.h | 3 +++ .../intel/cavs/include/cavs/drivers/dw-dma.h | 15 +++++++++++++++ src/platform/suecreek/include/platform/lib/shim.h | 3 +++ .../tigerlake/include/platform/lib/shim.h | 3 +++ 8 files changed, 39 insertions(+) diff --git a/src/platform/apollolake/include/platform/lib/shim.h b/src/platform/apollolake/include/platform/lib/shim.h index 9e213bcfe..756b61c69 100644 --- a/src/platform/apollolake/include/platform/lib/shim.h +++ b/src/platform/apollolake/include/platform/lib/shim.h @@ -209,6 +209,9 @@ #define SHIM_GPDMA_CHLLPC_EN BIT(5) #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x) +#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) +#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) + /** \brief LDO Control */ #define SHIM_LDOCTL 0xA4 #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) diff --git a/src/platform/baytrail/include/platform/drivers/dw-dma.h b/src/platform/baytrail/include/platform/drivers/dw-dma.h index 2060d3dfb..c05ca51e7 100644 --- a/src/platform/baytrail/include/platform/drivers/dw-dma.h +++ b/src/platform/baytrail/include/platform/drivers/dw-dma.h @@ -62,6 +62,10 @@ static inline void platform_dw_dma_llp_enable(struct dma *dma, static inline void platform_dw_dma_llp_disable(struct dma *dma, struct dma_chan_data *chan) { } +static inline void platform_dw_dma_llp_read(struct dma *dma, + struct dma_chan_data *chan, + uint32_t *llp_l, + uint32_t *llp_u) { } #endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */ #else diff --git a/src/platform/cannonlake/include/platform/lib/shim.h b/src/platform/cannonlake/include/platform/lib/shim.h index 3efce712b..53ee6f55a 100644 --- a/src/platform/cannonlake/include/platform/lib/shim.h +++ b/src/platform/cannonlake/include/platform/lib/shim.h @@ -211,6 +211,9 @@ #define SHIM_GPDMA_CHLLPC_EN BIT(7) #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) +#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) +#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) + #define L2LMCAP 0x71D00 #define L2MPAT 0x71D04 diff --git a/src/platform/haswell/include/platform/drivers/dw-dma.h b/src/platform/haswell/include/platform/drivers/dw-dma.h index c42ce8ecc..68addff64 100644 --- a/src/platform/haswell/include/platform/drivers/dw-dma.h +++ b/src/platform/haswell/include/platform/drivers/dw-dma.h @@ -60,6 +60,11 @@ static inline void platform_dw_dma_llp_enable(struct dma *dma, static inline void platform_dw_dma_llp_disable(struct dma *dma, struct dma_chan_data *chan) { } +static inline void platform_dw_dma_llp_read(struct dma *dma, + struct dma_chan_data *chan, + uint32_t *llp_l, + uint32_t *llp_u) { } + #endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */ #else diff --git a/src/platform/icelake/include/platform/lib/shim.h b/src/platform/icelake/include/platform/lib/shim.h index 61350e0db..0cc0917b2 100644 --- a/src/platform/icelake/include/platform/lib/shim.h +++ b/src/platform/icelake/include/platform/lib/shim.h @@ -205,6 +205,9 @@ #define SHIM_GPDMA_CHLLPC_EN BIT(7) #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) +#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) +#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) + #define L2LMCAP 0x71D00 #define L2MPAT 0x71D04 diff --git a/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h b/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h index b5306d62d..3c7026ad0 100644 --- a/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h +++ b/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h @@ -58,6 +58,12 @@ #define DW_CHLLPC(dma, chan) \ SHIM_GPDMA_CHLLPC((dma)->plat_data.id, (chan)->index) +#define DW_CHLLPL(dma, chan) \ + SHIM_GPDMA_CHLLPL((dma)->plat_data.id, (chan)->index) + +#define DW_CHLLPU(dma, chan) \ + SHIM_GPDMA_CHLLPU((dma)->plat_data.id, (chan)->index) + #define platform_dw_dma_set_class(chan, lli, class) \ (lli->ctrl_hi |= DW_CTLH_CLASS(class)) @@ -85,6 +91,15 @@ static inline void platform_dw_dma_llp_disable(struct dma *dma, shim_read(DW_CHLLPC(dma, chan)) & ~SHIM_GPDMA_CHLLPC_EN); } +static inline void platform_dw_dma_llp_read(struct dma *dma, + struct dma_chan_data *chan, + uint32_t *llp_l, + uint32_t *llp_u) +{ + *llp_l = shim_read(DW_CHLLPL(dma, chan)); + *llp_u = shim_read(DW_CHLLPU(dma, chan)); +} + static inline struct dw_lli *platform_dw_dma_lli_get(struct dw_lli *lli) { return cache_to_uncache(lli); diff --git a/src/platform/suecreek/include/platform/lib/shim.h b/src/platform/suecreek/include/platform/lib/shim.h index 5fd37d9cd..3f0951c85 100644 --- a/src/platform/suecreek/include/platform/lib/shim.h +++ b/src/platform/suecreek/include/platform/lib/shim.h @@ -200,6 +200,9 @@ #define SHIM_GPDMA_CHLLPC_EN BIT(7) #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) +#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) +#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) + #define L2LMCAP 0x71D00 #define L2MPAT 0x71D04 diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h index b76999ca8..64ffdf338 100644 --- a/src/platform/tigerlake/include/platform/lib/shim.h +++ b/src/platform/tigerlake/include/platform/lib/shim.h @@ -212,6 +212,9 @@ #define SHIM_GPDMA_CHLLPC_EN BIT(7) #define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) +#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) +#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) + /* I2S SHIM Registers */ #define I2SLCTL 0x71C04