mirror of https://github.com/thesofproject/sof.git
platform: mtk: add memory layout for mt8195
Add memory layout and register address for mtk mt8195
mt8195:
Cache
I-Cache: 32KB, 4-way Associativity
D-Cache: 128KB, 4-way Associativity
External Memory
DRAM: DSP can access DRAM which shared with CPU
L2TCM: 256KB DSP SRAM POOL
Currently, use
phy addr:0x60000000, size:0x1000000
dma phy addr: 0x61000000, size: 0x0100000
Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
This commit is contained in:
Allen-KH Cheng
Liam Girdwood
parent
0cad7a04fb
commit
b6b6fa23ce
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: YC Hung <yc.hung@mediatek.com>
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// Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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#ifndef MT_REG_BASE_H
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#define MT_REG_BASE_H
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#define MTK_DSP_IRQ_BASE 0x10009000
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#define MTK_DSP_IRQ_SIZE 0x1000
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#define MTK_TOPCKGEN_REG_BASE 0x1001B000
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#define MTK_TOPCKGEN_REG_SIZE 0x00001000
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#define MTK_DSP_REG_REMAP_BASE 0x10800000
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#define MTK_DSP_REG_REMAP_SIZE 0xE000
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#define MTK_DSP_TIMER_BASE 0x10800000
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#define MTK_DSP_UART0_BASE 0x10801000
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#define MTK_DSP_REG_BASE 0x10803000 /* DSPCFG base */
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#define MTK_DSP_WDT_BASE 0x10803400
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#define MTK_DSP_OSTIMER_BASE 0x1080D000
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#define MTK_DSP_JTAGMUX (MTK_DSP_REG_BASE + 0x0000)
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#define MTK_DSP_ALTRESETVEC (MTK_DSP_REG_BASE + 0x0004)
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#define MTK_DSP_PDEBUGDATA (MTK_DSP_REG_BASE + 0x0008)
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#define MTK_DSP_PDEBUGBUS0 (MTK_DSP_REG_BASE + 0x000c)
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#define MTK_DSP_PDEBUGBUS1 (MTK_DSP_REG_BASE + 0x0010)
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#define MTK_DSP_PDEBUGINST (MTK_DSP_REG_BASE + 0x0014)
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#define MTK_DSP_PDEBUGLS0STAT (MTK_DSP_REG_BASE + 0x0018)
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#define MTK_DSP_PDEBUGLS1STAT (MTK_DSP_REG_BASE + 0x001c)
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#define MTK_DSP_PDEBUGPC (MTK_DSP_REG_BASE + 0x0020)
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#define MTK_DSP_RESET_SW (MTK_DSP_REG_BASE + 0x0024)
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#define MTK_DSP_PFAULTBUS (MTK_DSP_REG_BASE + 0x0028)
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#define MTK_DSP_PFAULTINFO (MTK_DSP_REG_BASE + 0x002c)
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#define MTK_DSP_GPR00 (MTK_DSP_REG_BASE + 0x0030)
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#define MTK_DSP_GPR01 (MTK_DSP_REG_BASE + 0x0034)
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#define MTK_DSP_GPR02 (MTK_DSP_REG_BASE + 0x0038)
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#define MTK_DSP_GPR03 (MTK_DSP_REG_BASE + 0x003c)
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#define MTK_DSP_GPR04 (MTK_DSP_REG_BASE + 0x0040)
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#define MTK_DSP_GPR05 (MTK_DSP_REG_BASE + 0x0044)
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#define MTK_DSP_GPR06 (MTK_DSP_REG_BASE + 0x0048)
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#define MTK_DSP_GPR07 (MTK_DSP_REG_BASE + 0x004c)
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#define MTK_DSP_GPR08 (MTK_DSP_REG_BASE + 0x0050)
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#define MTK_DSP_GPR09 (MTK_DSP_REG_BASE + 0x0054)
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#define MTK_DSP_GPR0A (MTK_DSP_REG_BASE + 0x0058)
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#define MTK_DSP_GPR0B (MTK_DSP_REG_BASE + 0x005c)
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#define MTK_DSP_GPR0C (MTK_DSP_REG_BASE + 0x0060)
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#define MTK_DSP_GPR0D (MTK_DSP_REG_BASE + 0x0064)
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#define MTK_DSP_GPR0E (MTK_DSP_REG_BASE + 0x0068)
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#define MTK_DSP_GPR0F (MTK_DSP_REG_BASE + 0x006c)
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#define MTK_DSP_GPR10 (MTK_DSP_REG_BASE + 0x0070)
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#define MTK_DSP_GPR11 (MTK_DSP_REG_BASE + 0x0074)
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#define MTK_DSP_GPR12 (MTK_DSP_REG_BASE + 0x0078)
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#define MTK_DSP_GPR13 (MTK_DSP_REG_BASE + 0x007c)
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#define MTK_DSP_GPR14 (MTK_DSP_REG_BASE + 0x0080)
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#define MTK_DSP_GPR15 (MTK_DSP_REG_BASE + 0x0084)
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#define MTK_DSP_GPR16 (MTK_DSP_REG_BASE + 0x0088)
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#define MTK_DSP_GPR17 (MTK_DSP_REG_BASE + 0x008c)
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#define MTK_DSP_GPR18 (MTK_DSP_REG_BASE + 0x0090)
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#define MTK_DSP_GPR19 (MTK_DSP_REG_BASE + 0x0094)
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#define MTK_DSP_GPR1A (MTK_DSP_REG_BASE + 0x0098)
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#define MTK_DSP_GPR1B (MTK_DSP_REG_BASE + 0x009c)
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#define MTK_DSP_GPR1C (MTK_DSP_REG_BASE + 0x00a0)
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#define MTK_DSP_GPR1D (MTK_DSP_REG_BASE + 0x00a4)
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#define MTK_DSP_GPR1E (MTK_DSP_REG_BASE + 0x00a8)
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#define MTK_DSP_GPR1F (MTK_DSP_REG_BASE + 0x00ac)
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#define MTK_DSP_TCM_OFFSET (MTK_DSP_REG_BASE + 0x00b0) /* not used */
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#define MTK_DSP_DDR_OFFSET (MTK_DSP_REG_BASE + 0x00b4) /* not used */
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#define MTK_DSP_INTFDSP (MTK_DSP_REG_BASE + 0x00d0)
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#define MTK_DSP_INTFDSP_CLR (MTK_DSP_REG_BASE + 0x00d4)
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#define MTK_DSP_SRAM_PD_SW1 (MTK_DSP_REG_BASE + 0x00d8)
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#define MTK_DSP_SRAM_PD_SW2 (MTK_DSP_REG_BASE + 0x00dc)
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#define MTK_DSP_OCD (MTK_DSP_REG_BASE + 0x00e0)
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#define MTK_DSP_RG_DSP_IRQ_POL (MTK_DSP_REG_BASE + 0x00f0)
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#define MTK_DSP_DSP_IRQ_EN (MTK_DSP_REG_BASE + 0x00f4)
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#define MTK_DSP_DSP_IRQ_LEVEL (MTK_DSP_REG_BASE + 0x00f8)
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#define MTK_DSP_DSP_IRQ_STATUS (MTK_DSP_REG_BASE + 0x00fc)
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#define MTK_DSP_RG_INT2CIRQ (MTK_DSP_REG_BASE + 0x0114)
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#define MTK_DSP_RG_INT_POL_CTL0 (MTK_DSP_REG_BASE + 0x0120)
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#define MTK_DSP_RG_INT_EN_CTL0 (MTK_DSP_REG_BASE + 0x0130)
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#define MTK_DSP_RG_INT_LV_CTL0 (MTK_DSP_REG_BASE + 0x0140)
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#define MTK_DSP_RG_INT_STATUS0 (MTK_DSP_REG_BASE + 0x0150)
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#define MTK_DSP_PDEBUGSTATUS0 (MTK_DSP_REG_BASE + 0x0200)
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#define MTK_DSP_PDEBUGSTATUS1 (MTK_DSP_REG_BASE + 0x0204)
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#define MTK_DSP_PDEBUGSTATUS2 (MTK_DSP_REG_BASE + 0x0208)
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#define MTK_DSP_PDEBUGSTATUS3 (MTK_DSP_REG_BASE + 0x020c)
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#define MTK_DSP_PDEBUGSTATUS4 (MTK_DSP_REG_BASE + 0x0210)
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#define MTK_DSP_PDEBUGSTATUS5 (MTK_DSP_REG_BASE + 0x0214)
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#define MTK_DSP_PDEBUGSTATUS6 (MTK_DSP_REG_BASE + 0x0218)
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#define MTK_DSP_PDEBUGSTATUS7 (MTK_DSP_REG_BASE + 0x021c)
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#define MTK_DSP_DSP2PSRAM_PRIORITY (MTK_DSP_REG_BASE + 0x0220) /* not used */
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#define MTK_DSP_AUDIO_DSP2SPM_INT (MTK_DSP_REG_BASE + 0x0224)
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#define MTK_DSP_AUDIO_DSP2SPM_INT_ACK (MTK_DSP_REG_BASE + 0x0228)
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#define MTK_DSP_AUDIO_DSP_DEBUG_SEL (MTK_DSP_REG_BASE + 0x022C)
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#define MTK_DSP_AUDIO_DSP_EMI_BASE_ADDR (MTK_DSP_REG_BASE + 0x02E0) /* not used */
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#define MTK_DSP_AUDIO_DSP_SHARED_IRAM (MTK_DSP_REG_BASE + 0x02E4)
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#define MTK_DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON (MTK_DSP_REG_BASE + 0x02F0)
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#define MTK_DSP_RG_SEMAPHORE00 (MTK_DSP_REG_BASE + 0x0300)
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#define MTK_DSP_RG_SEMAPHORE01 (MTK_DSP_REG_BASE + 0x0304)
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#define MTK_DSP_RG_SEMAPHORE02 (MTK_DSP_REG_BASE + 0x0308)
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#define MTK_DSP_RG_SEMAPHORE03 (MTK_DSP_REG_BASE + 0x030C)
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#define MTK_DSP_RG_SEMAPHORE04 (MTK_DSP_REG_BASE + 0x0310)
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#define MTK_DSP_RG_SEMAPHORE05 (MTK_DSP_REG_BASE + 0x0314)
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#define MTK_DSP_RG_SEMAPHORE06 (MTK_DSP_REG_BASE + 0x0318)
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#define MTK_DSP_RG_SEMAPHORE07 (MTK_DSP_REG_BASE + 0x031C)
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#define MTK_DSP_RESERVED_0 (MTK_DSP_REG_BASE + 0x03F0)
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#define MTK_DSP_RESERVED_1 (MTK_DSP_REG_BASE + 0x03F4)
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/*MBOX registers*/
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#define MTK_DSP_MBOX_REG_BASE(x) (0x10816000 + (0x1000 * (x)))
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#define MTK_DSP_MBOX_REG_SIZE (0x5000)
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#define MTK_DSP_MBOX_IN_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x0)
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#define MTK_DSP_MBOX_IN_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x04)
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#define MTK_DSP_MBOX_OUT_CMD(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x1c)
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#define MTK_DSP_MBOX_OUT_CMD_CLR(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x20)
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#define MTK_DSP_MBOX_OUT_CMD_MSG0(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x24)
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#define MTK_DSP_MBOX_OUT_CMD_MSG1(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x28)
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#define MTK_DSP_MBOX_OUT_CMD_MSG2(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x2c)
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#define MTK_DSP_MBOX_OUT_CMD_MSG3(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x30)
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#define MTK_DSP_MBOX_OUT_CMD_MSG4(x) (MTK_DSP_MBOX_REG_BASE(x) + 0x34)
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/* Redefinition for using Special registers */
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#define MTK_TICKLESS_STATUS_REG (DSP_RESERVED_1)
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/* WDT CONFIGS */
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#define MTK_ADSP_WDT_MODE (MTK_DSP_WDT_BASE + 0x00)
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#define MTK_ADSP_WDT_LENGTH (MTK_DSP_WDT_BASE + 0x04)
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#define MTK_ADSP_WDT_RESTART (MTK_DSP_WDT_BASE + 0x08)
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#define MTK_ADSP_WDT_STA (MTK_DSP_WDT_BASE + 0x0C)
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#define MTK_ADSP_WDT_SWRST (MTK_DSP_WDT_BASE + 0x14)
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#define MTK_ADSP_WDT_SWRST_KEY 0x1209
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#define MTK_ADSP_WDT_RESTART_RELOAD 0x1971
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#define MTK_ADSP_WDT_LENGTH_KEY 0x8
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#define MTK_WDT_LENGTH_TIMEOUT(n) ((n) << 5)
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#endif /* MT_REG_BASE_H */
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: YC Hung <yc.hung@mediatek.com>
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// Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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#ifdef __SOF_LIB_MEMORY_H__
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#ifndef __PLATFORM_LIB_MEMORY_H__
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#define __PLATFORM_LIB_MEMORY_H__
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#include <sof/lib/cache.h>
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#include <xtensa/config/core-isa.h>
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#define BOOT_WITH_DRAM /*Use DRAM as SRAM1 for heap related*/
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/* data cache line alignment */
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#define PLATFORM_DCACHE_ALIGN sizeof(void *)
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/* BOOT_WITH_DRAM ONLY */
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/* physical DSP addresses */
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#define DRAM_BASE 0x60000000
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#define DRAM_AUDIO_SHARED_SIZE 0x80000
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#define DRAM_SIZE 0x1000000 /*DRAM Size : 16M , need to sync with Host side*/
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#define SRAM_TOTAL_SIZE 0x40000 /*256KB DSP SRAM*/
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#define VECTOR_SIZE 0x628
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#define SRAM0_BASE DRAM_BASE
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#define SRAM0_SIZE (DRAM_SIZE >> 1)
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#define SRAM1_BASE (DRAM_BASE + SRAM0_SIZE)
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#define SRAM1_SIZE \
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(DRAM_SIZE - SRAM0_SIZE - DRAM_AUDIO_SHARED_SIZE - UUID_ENTRY_ELF_SIZE - \
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LOG_ENTRY_ELF_SIZE - EXT_MANIFEST_ELF_SIZE)
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#define DMA_SIZE 0x100000
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#define UUID_ENTRY_ELF_SIZE 0x6000
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#define LOG_ENTRY_ELF_SIZE 0x200000
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#define EXT_MANIFEST_ELF_SIZE 0x100000
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#define UUID_ENTRY_ELF_BASE (SRAM1_BASE + SRAM1_SIZE)
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#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
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#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
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/*
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* The Heap and Stack on MT8195 are organised like this :-
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*
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* +--------------------------------------------------------------------------+
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* | Offset | Region | Size |
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* +---------------------+----------------+-----------------------------------+
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* | SRAM1_BASE | RO Data | SOF_DATA_SIZE |
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* | | Data | |
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* | | BSS | |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_BASE | | |
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* +---------------------+----------------+-----------------------------------+
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*/
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/* Mailbox configuration */
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#define SRAM_OUTBOX_BASE SRAM1_BASE
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#define SRAM_OUTBOX_SIZE 0x1000
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#define SRAM_OUTBOX_OFFSET 0
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#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
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#define SRAM_INBOX_SIZE 0x1000
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#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
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#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
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#define SRAM_DEBUG_SIZE 0x800
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#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
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#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
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#define SRAM_EXCEPT_SIZE 0x800
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#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
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#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
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#define SRAM_STREAM_SIZE 0x1000
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#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
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#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
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#define SRAM_TRACE_SIZE 0x1000
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#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
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/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
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#define SOF_MAILBOX_SIZE \
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(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE + \
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SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
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/* Heap section sizes for module pool */
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#define HEAP_RT_COUNT8 0
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#define HEAP_RT_COUNT16 48
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#define HEAP_RT_COUNT32 48
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#define HEAP_RT_COUNT64 32
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#define HEAP_RT_COUNT128 32
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#define HEAP_RT_COUNT256 32
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#define HEAP_RT_COUNT512 4
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#define HEAP_RT_COUNT1024 4
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#define HEAP_RT_COUNT2048 2
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#define HEAP_RT_COUNT4096 2
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/* Heap section sizes for system runtime heap */
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#define HEAP_SYS_RT_COUNT64 128
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#define HEAP_SYS_RT_COUNT512 16
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#define HEAP_SYS_RT_COUNT1024 8
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/* Heap configuration */
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#define HEAP_SYSTEM_BASE (SRAM1_BASE + SOF_MAILBOX_SIZE)
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#define HEAP_SYSTEM_SIZE 0x6000
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#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE
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#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
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/*24KB*/
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#define HEAP_SYS_RUNTIME_SIZE \
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(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + HEAP_SYS_RT_COUNT1024 * 1024)
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#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
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/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
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#define HEAP_RUNTIME_SIZE \
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(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
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HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512 + \
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HEAP_RT_COUNT1024 * 1024 + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
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#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
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#define HEAP_BUFFER_SIZE \
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(SRAM1_SIZE - SOF_MAILBOX_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \
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HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
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#define HEAP_BUFFER_BLOCK_SIZE 0x100
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#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
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#define PLATFORM_HEAP_SYSTEM 1 /* one per core */
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#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */
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#define PLATFORM_HEAP_RUNTIME 1
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#define PLATFORM_HEAP_BUFFER 1
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/* Stack configuration */
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#define SOF_STACK_SIZE 0x8000
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#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/
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#define SOF_STACK_BASE (SRAM1_BASE + SRAM1_SIZE)
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#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
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/* Vector and literal sizes - not in core-isa.h */
|
||||
#define SOF_MEM_VECT_LIT_SIZE 0x4
|
||||
#define SOF_MEM_VECT_TEXT_SIZE 0x1c
|
||||
#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
|
||||
|
||||
#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
|
||||
#define SOF_MEM_RESET_LIT_SIZE 0x120
|
||||
#define SOF_MEM_VECBASE_LIT_SIZE 0x178
|
||||
|
||||
#define SOF_MEM_RO_SIZE 0x8
|
||||
|
||||
#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE
|
||||
|
||||
/** \brief EDF task's default stack size in bytes. */
|
||||
#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
|
||||
|
||||
#if !defined(__ASSEMBLER__) && !defined(LINKER)
|
||||
|
||||
struct sof;
|
||||
|
||||
/**
|
||||
* \brief Data shared between different cores.
|
||||
* Does nothing, since mt8195 doesn't support SMP.
|
||||
*/
|
||||
#define SHARED_DATA
|
||||
|
||||
void platform_init_memmap(struct sof *sof);
|
||||
|
||||
static inline void *platform_shared_get(void *ptr, int bytes)
|
||||
{
|
||||
return ptr;
|
||||
}
|
||||
|
||||
#define uncache_to_cache(address) address
|
||||
#define cache_to_uncache(address) address
|
||||
#define is_uncached(address) 0
|
||||
|
||||
/**
|
||||
* \brief Function for keeping shared data synchronized.
|
||||
* It's used after usage of data shared by different cores.
|
||||
* Such data is either statically marked with SHARED_DATA
|
||||
* or dynamically allocated with SOF_MEM_FLAG_SHARED flag.
|
||||
* Does nothing, since mt8195 doesn't support SMP.
|
||||
*/
|
||||
|
||||
static inline void *platform_rfree_prepare(void *ptr)
|
||||
{
|
||||
return ptr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define host_to_local(addr) (addr)
|
||||
#define local_to_host(addr) (addr)
|
||||
|
||||
#endif /* __PLATFORM_LIB_MEMORY_H__ */
|
||||
|
||||
#else
|
||||
|
||||
#error "This file shouldn't be included from outside of sof/lib/memory.h"
|
||||
|
||||
#endif /* __SOF_LIB_MEMORY_H__ */
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
//
|
||||
// Copyright(c) 2021 Mediatek
|
||||
//
|
||||
// Author: YC Hung <yc.hung@mediatek.com>
|
||||
|
||||
#include <sof/common.h>
|
||||
#include <sof/lib/mm_heap.h>
|
||||
#include <sof/lib/memory.h>
|
||||
#include <sof/sof.h>
|
||||
#include <ipc/topology.h>
|
||||
|
||||
/* Heap blocks for system runtime */
|
||||
static SHARED_DATA struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64];
|
||||
static SHARED_DATA struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512];
|
||||
static SHARED_DATA struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024];
|
||||
|
||||
/* Heap memory for system runtime */
|
||||
static SHARED_DATA struct block_map sys_rt_heap_map[] = {
|
||||
BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64),
|
||||
BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512),
|
||||
BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024),
|
||||
};
|
||||
|
||||
/* Heap blocks for modules */
|
||||
static SHARED_DATA struct block_hdr mod_block16[HEAP_RT_COUNT16];
|
||||
static SHARED_DATA struct block_hdr mod_block32[HEAP_RT_COUNT32];
|
||||
static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64];
|
||||
static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128];
|
||||
static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256];
|
||||
static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512];
|
||||
static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024];
|
||||
static SHARED_DATA struct block_hdr mod_block2048[HEAP_RT_COUNT2048];
|
||||
static SHARED_DATA struct block_hdr mod_block4096[HEAP_RT_COUNT4096];
|
||||
|
||||
/* Heap memory map for modules */
|
||||
static SHARED_DATA struct block_map rt_heap_map[] = {
|
||||
BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16),
|
||||
BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32),
|
||||
BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64),
|
||||
BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128),
|
||||
BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256),
|
||||
BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512),
|
||||
BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024),
|
||||
BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048),
|
||||
BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096),
|
||||
};
|
||||
|
||||
/* Heap blocks for buffers */
|
||||
static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT];
|
||||
|
||||
/* Heap memory map for buffers */
|
||||
static SHARED_DATA struct block_map buf_heap_map[] = {
|
||||
BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block),
|
||||
};
|
||||
|
||||
static SHARED_DATA struct mm memmap = {
|
||||
.system[0] = {
|
||||
.heap = HEAP_SYSTEM_BASE,
|
||||
.size = HEAP_SYSTEM_SIZE,
|
||||
.info = {.free = HEAP_SYSTEM_SIZE,},
|
||||
.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
|
||||
SOF_MEM_CAPS_DMA,
|
||||
},
|
||||
.system_runtime[0] = {
|
||||
.blocks = ARRAY_SIZE(sys_rt_heap_map),
|
||||
.map = sys_rt_heap_map,
|
||||
.heap = HEAP_SYS_RUNTIME_BASE,
|
||||
.size = HEAP_SYS_RUNTIME_SIZE,
|
||||
.info = {.free = HEAP_SYS_RUNTIME_SIZE,},
|
||||
.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
|
||||
SOF_MEM_CAPS_DMA,
|
||||
},
|
||||
.runtime[0] = {
|
||||
.blocks = ARRAY_SIZE(rt_heap_map),
|
||||
.map = rt_heap_map,
|
||||
.heap = HEAP_RUNTIME_BASE,
|
||||
.size = HEAP_RUNTIME_SIZE,
|
||||
.info = {.free = HEAP_RUNTIME_SIZE,},
|
||||
.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
|
||||
SOF_MEM_CAPS_DMA,
|
||||
},
|
||||
.buffer[0] = {
|
||||
.blocks = ARRAY_SIZE(buf_heap_map),
|
||||
.map = buf_heap_map,
|
||||
.heap = HEAP_BUFFER_BASE,
|
||||
.size = HEAP_BUFFER_SIZE,
|
||||
.info = {.free = HEAP_BUFFER_SIZE,},
|
||||
.caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE |
|
||||
SOF_MEM_CAPS_DMA,
|
||||
},
|
||||
.total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE +
|
||||
HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,},
|
||||
};
|
||||
|
||||
void platform_init_memmap(struct sof *sof)
|
||||
{
|
||||
/* memmap has been initialized statically as a part of .data */
|
||||
sof->memory_map = &memmap;
|
||||
}
|
||||
|
|
@ -0,0 +1,497 @@
|
|||
/*
|
||||
* Linker Script for mt8195 Mediatek
|
||||
*
|
||||
* This script is run through the GNU C preprocessor to align the memory
|
||||
* offsets with headers.
|
||||
*
|
||||
* Use spaces for formatting as cpp ignore tab sizes.
|
||||
*/
|
||||
|
||||
|
||||
#include <sof/lib/memory.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
|
||||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
vector_reset_text :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR,
|
||||
len = SOF_MEM_RESET_TEXT_SIZE
|
||||
vector_reset_lit :
|
||||
org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE,
|
||||
len = SOF_MEM_RESET_LIT_SIZE
|
||||
vector_base_text :
|
||||
org = XCHAL_VECBASE_RESET_PADDR,
|
||||
len = SOF_MEM_VECBASE_LIT_SIZE
|
||||
vector_int2_lit :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_int2_text :
|
||||
org = XCHAL_INTLEVEL2_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
vector_int3_lit :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_int3_text :
|
||||
org = XCHAL_INTLEVEL3_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
vector_int4_lit :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_int4_text :
|
||||
org = XCHAL_INTLEVEL4_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
vector_kernel_lit :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_kernel_text :
|
||||
org = XCHAL_KERNEL_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
vector_user_lit :
|
||||
org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_user_text :
|
||||
org = XCHAL_USER_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
vector_double_lit :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE,
|
||||
len = SOF_MEM_VECT_LIT_SIZE
|
||||
vector_double_text :
|
||||
org = XCHAL_DOUBLEEXC_VECTOR_PADDR,
|
||||
len = SOF_MEM_VECT_TEXT_SIZE
|
||||
sof_sram0 :
|
||||
org = SRAM0_BASE,
|
||||
len = SRAM0_SIZE
|
||||
sof_sram1 :
|
||||
org = SRAM1_BASE,
|
||||
len = SRAM1_SIZE
|
||||
system_heap :
|
||||
org = HEAP_SYSTEM_BASE,
|
||||
len = HEAP_SYSTEM_SIZE
|
||||
system_runtime_heap :
|
||||
org = HEAP_SYS_RUNTIME_BASE,
|
||||
len = HEAP_SYS_RUNTIME_SIZE
|
||||
runtime_heap :
|
||||
org = HEAP_RUNTIME_BASE,
|
||||
len = HEAP_RUNTIME_SIZE
|
||||
buffer_heap :
|
||||
org = HEAP_BUFFER_BASE,
|
||||
len = HEAP_BUFFER_SIZE
|
||||
sof_stack :
|
||||
org = SOF_STACK_END,
|
||||
len = SOF_STACK_BASE - SOF_STACK_END
|
||||
static_uuid_entries_seg (!ari) :
|
||||
org = UUID_ENTRY_ELF_BASE,
|
||||
len = UUID_ENTRY_ELF_SIZE
|
||||
static_log_entries_seg (!ari) :
|
||||
org = LOG_ENTRY_ELF_BASE,
|
||||
len = LOG_ENTRY_ELF_SIZE
|
||||
fw_metadata_seg (!ari) :
|
||||
org = EXT_MANIFEST_ELF_BASE,
|
||||
len = EXT_MANIFEST_ELF_SIZE
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
vector_reset_text_phdr PT_LOAD;
|
||||
vector_reset_lit_phdr PT_LOAD;
|
||||
vector_base_text_phdr PT_LOAD;
|
||||
vector_base_lit_phdr PT_LOAD;
|
||||
vector_int2_text_phdr PT_LOAD;
|
||||
vector_int2_lit_phdr PT_LOAD;
|
||||
vector_int3_text_phdr PT_LOAD;
|
||||
vector_int3_lit_phdr PT_LOAD;
|
||||
vector_int4_text_phdr PT_LOAD;
|
||||
vector_int4_lit_phdr PT_LOAD;
|
||||
vector_kernel_text_phdr PT_LOAD;
|
||||
vector_kernel_lit_phdr PT_LOAD;
|
||||
vector_user_text_phdr PT_LOAD;
|
||||
vector_user_lit_phdr PT_LOAD;
|
||||
vector_double_text_phdr PT_LOAD;
|
||||
vector_double_lit_phdr PT_LOAD;
|
||||
sof_sram0_phdr PT_LOAD;
|
||||
sof_sram1_phdr PT_LOAD;
|
||||
system_heap_phdr PT_LOAD;
|
||||
system_runtime_heap_phdr PT_LOAD;
|
||||
runtime_heap_phdr PT_LOAD;
|
||||
buffer_heap_phdr PT_LOAD;
|
||||
sof_stack_phdr PT_LOAD;
|
||||
static_uuid_entries_phdr PT_NOTE;
|
||||
static_log_entries_phdr PT_NOTE;
|
||||
metadata_entries_phdr PT_NOTE;
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(_ResetVector)
|
||||
_rom_store_table = 0;
|
||||
|
||||
/* ABI0 does not use Window base */
|
||||
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
|
||||
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x00000100;
|
||||
_memmap_cacheattr_wt_base = 0x00000300;
|
||||
_memmap_cacheattr_bp_base = 0x00000400;
|
||||
_memmap_cacheattr_unused_mask = 0xFFFFF0FF;
|
||||
_memmap_cacheattr_wb_trapnull = 0x44444140;
|
||||
_memmap_cacheattr_wba_trapnull = 0x44444140;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x44444240;
|
||||
_memmap_cacheattr_wt_trapnull = 0x44444340;
|
||||
_memmap_cacheattr_bp_trapnull = 0x44444440;
|
||||
_memmap_cacheattr_wb_strict = 0x00000100;
|
||||
_memmap_cacheattr_wt_strict = 0x00000300;
|
||||
_memmap_cacheattr_bp_strict = 0x00000400;
|
||||
_memmap_cacheattr_wb_allvalid = 0x44444144;
|
||||
_memmap_cacheattr_wt_allvalid = 0x44444344;
|
||||
_memmap_cacheattr_bp_allvalid = 0x44444444;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
|
||||
|
||||
_EXT_MAN_ALIGN_ = 16;
|
||||
EXTERN(ext_man_fw_ver)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.ResetVector.text : ALIGN(4)
|
||||
{
|
||||
_ResetVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.ResetVector.text))
|
||||
_ResetVector_text_end = ABSOLUTE(.);
|
||||
} >vector_reset_text :vector_reset_text_phdr
|
||||
|
||||
.ResetVector.literal : ALIGN(4)
|
||||
{
|
||||
_ResetVector_literal_start = ABSOLUTE(.);
|
||||
*(.ResetVector.literal)
|
||||
_ResetVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_reset_lit :vector_reset_lit_phdr
|
||||
|
||||
.WindowVectors.text : ALIGN(4)
|
||||
{
|
||||
_WindowVectors_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.WindowVectors.text))
|
||||
_WindowVectors_text_end = ABSOLUTE(.);
|
||||
} >vector_base_text :vector_base_text_phdr
|
||||
|
||||
.Level2InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level2InterruptVector.literal)
|
||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int2_lit :vector_int2_lit_phdr
|
||||
|
||||
.Level2InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level2InterruptVector.text))
|
||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int2_text :vector_int2_text_phdr
|
||||
|
||||
.Level3InterruptVector.literal : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||
*(.Level3InterruptVector.literal)
|
||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int3_lit :vector_int3_lit_phdr
|
||||
|
||||
.Level3InterruptVector.text : ALIGN(4)
|
||||
{
|
||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.Level3InterruptVector.text))
|
||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int3_text :vector_int3_text_phdr
|
||||
|
||||
.DebugExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DebugExceptionVector.literal)
|
||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_int4_lit :vector_int4_lit_phdr
|
||||
|
||||
.DebugExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DebugExceptionVector.text))
|
||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_int4_text :vector_int4_text_phdr
|
||||
|
||||
.KernelExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.KernelExceptionVector.literal)
|
||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||
|
||||
.KernelExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.KernelExceptionVector.text))
|
||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_kernel_text :vector_kernel_text_phdr
|
||||
|
||||
.UserExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.UserExceptionVector.literal)
|
||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_user_lit :vector_user_lit_phdr
|
||||
|
||||
.UserExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.UserExceptionVector.text))
|
||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_user_text :vector_user_text_phdr
|
||||
|
||||
.DoubleExceptionVector.literal : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||
*(.DoubleExceptionVector.literal)
|
||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||
} >vector_double_lit :vector_double_lit_phdr
|
||||
|
||||
.DoubleExceptionVector.text : ALIGN(4)
|
||||
{
|
||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.DoubleExceptionVector.text))
|
||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||
} >vector_double_text :vector_double_text_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
/* C++ constructor and destructor tables, properly ordered: */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.module_init : ALIGN(4)
|
||||
{
|
||||
_module_init_start = ABSOLUTE(.);
|
||||
*(*.module_init)
|
||||
_module_init_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.reset.rodata : ALIGN(4)
|
||||
{
|
||||
_reset_rodata_start = ABSOLUTE(.);
|
||||
*(.reset.rodata)
|
||||
_reset_rodata_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_trace_ctx_start = ABSOLUTE(.);
|
||||
*(.trace_ctx)
|
||||
_trace_ctx_end = ABSOLUTE(.);
|
||||
_data_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
/* stack */
|
||||
_end = SOF_STACK_END;
|
||||
PROVIDE(end = SOF_STACK_END);
|
||||
_stack_sentry = SOF_STACK_END;
|
||||
__stack = SOF_STACK_BASE;
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
|
||||
.system_heap (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (32);
|
||||
_system_heap_start = ABSOLUTE(.);
|
||||
. = . + HEAP_SYSTEM_SIZE;
|
||||
_system_heap_end = ABSOLUTE(.);
|
||||
} >system_heap :system_heap_phdr
|
||||
|
||||
.system_runtime_heap (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (HEAP_BUF_ALIGNMENT);
|
||||
_system_runtime_heap_start = ABSOLUTE(.);
|
||||
. = . + HEAP_SYS_RUNTIME_SIZE;
|
||||
_system_runtime_heap_end = ABSOLUTE(.);
|
||||
} >system_runtime_heap :system_runtime_heap_phdr
|
||||
|
||||
.runtime_heap (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (32);
|
||||
_runtime_heap_start = ABSOLUTE(.);
|
||||
. = . + HEAP_RUNTIME_SIZE;
|
||||
_runtime_heap_end = ABSOLUTE(.);
|
||||
} >runtime_heap :runtime_heap_phdr
|
||||
|
||||
.buffer_heap (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (HEAP_BUF_ALIGNMENT);
|
||||
_buffer_heap_start = ABSOLUTE(.);
|
||||
. = . + HEAP_BUFFER_SIZE;
|
||||
_buffer_heap_end = ABSOLUTE(.);
|
||||
} >buffer_heap :buffer_heap_phdr
|
||||
|
||||
.sof_stack (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (4096);
|
||||
_sof_stack_start = ABSOLUTE(.);
|
||||
. = . + SOF_STACK_TOTAL_SIZE;
|
||||
_sof_stack_end = ABSOLUTE(.);
|
||||
} >sof_stack :sof_stack_phdr
|
||||
|
||||
.static_uuid_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_uuids)
|
||||
} > static_uuid_entries_seg :static_uuid_entries_phdr
|
||||
|
||||
.static_log_entries (COPY) : ALIGN(1024)
|
||||
{
|
||||
*(*.static_log*)
|
||||
} > static_log_entries_seg :static_log_entries_phdr
|
||||
|
||||
.fw_ready : ALIGN(4)
|
||||
{
|
||||
KEEP (*(.fw_ready))
|
||||
KEEP (*(.fw_ready_metadata))
|
||||
} >sof_sram0 :sof_sram0_phdr
|
||||
|
||||
.fw_metadata (COPY) : ALIGN(1024)
|
||||
{
|
||||
KEEP (*(.fw_metadata))
|
||||
. = ALIGN(_EXT_MAN_ALIGN_);
|
||||
} >fw_metadata_seg :metadata_entries_phdr
|
||||
}
|
||||
Loading…
Reference in New Issue