mirror of https://github.com/thesofproject/sof.git
drivers: mtk: add drivers for mt8195
Add irq, ipc and timer drivers for mtk mt8195 About mt8195: Two domains of IRQ: IRQ_EXT_DOMAIN0 and IRQ_EXT_DOMAIN1 IRQ num: 25 interrupts IPC: use mbx0 and mbx1 to transfer ipc msg Signed-off-by: YC Hung <yc.hung@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
This commit is contained in:
Allen-KH Cheng
Liam Girdwood
parent
ef37ebaabf
commit
0cad7a04fb
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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#include <sof/common.h>
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#include <sof/bit.h>
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#include <sof/drivers/interrupt.h>
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#include <sof/lib/cpu.h>
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#include <sof/lib/io.h>
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#include <sof/lib/memory.h>
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#include <sof/lib/uuid.h>
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#include <sof/list.h>
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#include <sof/spinlock.h>
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#include <errno.h>
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#include <inttypes.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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/* fa00558c-d653-4851-a03a-b21f125a9524 */
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DECLARE_SOF_UUID("irq-mt8195", irq_mt8195_uuid, 0xfa00558c, 0xd653, 0x4851,
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0xa0, 0x3a, 0xb2, 0x1f, 0x12, 0x5a, 0x95, 0x24);
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DECLARE_TR_CTX(int_tr, SOF_UUID(irq_mt8195_uuid), LOG_LEVEL_INFO);
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/* os timer reg value * 77ns 13M os timer
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* 1 ms: 12987* 1.5ms: 19436
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* 2 ms: 25974* 3 ms: 38961
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*/
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static void irq_mask_all(void)
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{
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io_reg_update_bits(RG_DSP_IRQ_EN, 0xffffffff, 0x0);
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io_reg_update_bits(DSP_IRQ_EN, 0xffffffff, 0x0);
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}
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static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core)
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{
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int32_t in_irq, level;
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if (!desc) {
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level = GET_INTLEVEL(irq);
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in_irq = GET_INTERRUPT_ID(irq);
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if (level > MAX_IRQ_NUM) {
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tr_err(&int_tr, "Invalid interrupt %d", irq);
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return;
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}
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io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), 0x0);
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} else {
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switch (desc->irq) {
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case IRQ_EXT_DOMAIN0:
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io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET), 0x0);
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break;
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case IRQ_EXT_DOMAIN1:
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io_reg_update_bits(DSP_IRQ_EN, BIT(irq), 0x0);
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break;
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default:
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tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
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return;
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}
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}
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}
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static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core)
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{
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int32_t in_irq, level;
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if (!desc) {
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level = GET_INTLEVEL(irq);
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in_irq = GET_INTERRUPT_ID(irq);
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if (level > MAX_IRQ_NUM) {
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tr_err(&int_tr, "Invalid interrupt %d", irq);
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return;
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}
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io_reg_update_bits(RG_DSP_IRQ_EN, BIT(in_irq), BIT(in_irq));
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} else {
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switch (desc->irq) {
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case IRQ_EXT_DOMAIN0:
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io_reg_update_bits(RG_DSP_IRQ_EN, BIT(irq + IRQ_EXT_DOMAIN0_OFFSET),
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BIT(irq + IRQ_EXT_DOMAIN0_OFFSET));
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break;
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case IRQ_EXT_DOMAIN1:
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io_reg_update_bits(DSP_IRQ_EN, BIT(irq), BIT(irq));
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break;
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default:
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tr_err(&int_tr, "Invalid interrupt %d", desc->irq);
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return;
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}
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}
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}
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static uint64_t mtk_get_irq_interrupts(uint32_t irq)
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{
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uint32_t irq_status;
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switch (irq) {
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case IRQ_NUM_EXT_LEVEL23:
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irq_status = io_reg_read(DSP_IRQ_STATUS);
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irq_status &= IRQ_EXT_DOMAIN2_MASK;
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break;
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default:
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irq_status = io_reg_read(RG_DSP_IRQ_STATUS);
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irq_status &= IRQ_EXT_DOMAIN1_MASK;
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break;
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}
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return irq_status;
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}
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static int get_first_irq(uint64_t ints)
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{
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return ffs(ints) - 1;
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}
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static inline void mtk_handle_irq(struct irq_cascade_desc *cascade,
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uint32_t line_index, uint64_t status)
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{
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int core = cpu_get_id();
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struct list_item *clist;
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struct irq_desc *child = NULL;
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int bit;
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bool handled;
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while (status) {
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bit = get_first_irq(status);
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handled = false;
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status &= ~(1ull << bit);
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spin_lock(&cascade->lock);
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list_for_item(clist, &cascade->child[bit].list) {
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child = container_of(clist, struct irq_desc, irq_list);
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if (child->handler && (child->cpu_mask & 1 << core)) {
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child->handler(child->handler_arg);
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handled = true;
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}
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}
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spin_unlock(&cascade->lock);
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if (!handled) {
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tr_err(&int_tr, "irq_handler(): not handled, bit %d", bit);
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if (line_index == IRQ_NUM_EXT_LEVEL23)
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io_reg_update_bits(DSP_IRQ_EN, BIT(bit), 0x0);
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else
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io_reg_update_bits(RG_DSP_IRQ_EN, BIT(bit), 0x0);
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}
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}
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}
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static inline void irq_handler(void *data, uint32_t line_index)
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{
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struct irq_desc *parent = data;
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struct irq_cascade_desc *cascade =
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container_of(parent, struct irq_cascade_desc, desc);
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uint64_t status;
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status = mtk_get_irq_interrupts(line_index);
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if (status)
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/* Handle current interrupts */
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mtk_handle_irq(cascade, line_index, status);
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else
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tr_err(&int_tr, "invalid interrupt status");
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}
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#define DEFINE_IRQ_HANDLER(n) \
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static void irqhandler_##n(void *arg) \
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{ \
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irq_handler(arg, n); \
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}
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DEFINE_IRQ_HANDLER(1)
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DEFINE_IRQ_HANDLER(23)
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static const char mtk_irq_ext_domain0[] = "mtk_irq_ext_domain0";
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static const char mtk_irq_ext_domain1[] = "mtk_irq_ext_domain1";
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static const struct irq_cascade_ops irq_ops = {
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.mask = mtk_irq_mask,
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.unmask = mtk_irq_unmask,
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};
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static const struct irq_cascade_tmpl dsp_irq[] = {
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{
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.name = mtk_irq_ext_domain0,
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.irq = IRQ_NUM_EXT_LEVEL01,
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.handler = irqhandler_1,
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.ops = &irq_ops,
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.global_mask = false,
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},
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{
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.name = mtk_irq_ext_domain1,
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.irq = IRQ_NUM_EXT_LEVEL23,
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.handler = irqhandler_23,
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.ops = &irq_ops,
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.global_mask = false,
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},
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};
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uint32_t mtk_get_irq_domain_id(int32_t irq)
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{
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uint32_t in_irq = GET_INTERRUPT_ID(irq);
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int32_t level = GET_INTLEVEL(irq);
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if (in_irq >= DOMAIN1_MAX_IRQ_NUM)
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in_irq -= DOMAIN1_MAX_IRQ_NUM;
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if (level == IRQ_EXT_DOMAIN0)
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return interrupt_get_irq(in_irq, dsp_irq[0].name);
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else
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return interrupt_get_irq(in_irq, dsp_irq[1].name);
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}
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void platform_interrupt_init(void)
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{
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int i;
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irq_mask_all();
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for (i = 0; i < ARRAY_SIZE(dsp_irq); i++)
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interrupt_cascade_register(dsp_irq + i);
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}
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void platform_interrupt_set(uint32_t irq)
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{
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if (interrupt_is_dsp_direct(irq))
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arch_interrupt_set(irq);
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}
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void platform_interrupt_clear(uint32_t irq, uint32_t mask)
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{
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if (interrupt_is_dsp_direct(irq))
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arch_interrupt_clear(irq);
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}
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uint32_t platform_interrupt_get_enabled(void)
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{
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return 0;
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}
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void interrupt_mask(uint32_t irq, unsigned int cpu)
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{
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struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
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if (cascade && cascade->ops->mask)
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cascade->ops->mask(&cascade->desc, irq - cascade->irq_base,
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cpu);
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else
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mtk_irq_mask(NULL, irq, 0);
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}
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void interrupt_unmask(uint32_t irq, unsigned int cpu)
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{
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struct irq_cascade_desc *cascade = interrupt_get_parent(irq);
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if (cascade && cascade->ops->unmask)
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cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base,
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cpu);
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else
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mtk_irq_unmask(NULL, irq, 0);
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}
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@ -0,0 +1,156 @@
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
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#include <sof/debug/panic.h>
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#include <sof/drivers/interrupt.h>
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#include <sof/ipc/driver.h>
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#include <sof/ipc/msg.h>
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#include <sof/ipc/schedule.h>
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#include <sof/lib/alloc.h>
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#include <sof/lib/dma.h>
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#include <sof/lib/mailbox.h>
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#include <sof/lib/memory.h>
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#include <sof/lib/uuid.h>
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#include <sof/lib/wait.h>
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#include <sof/list.h>
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#include <sof/platform.h>
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#include <sof/schedule/edf_schedule.h>
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#include <sof/schedule/schedule.h>
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#include <sof/schedule/task.h>
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#include <sof/spinlock.h>
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#include <ipc/header.h>
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#include <ipc/topology.h>
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#include <ipc/trace.h>
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#include <platform/drivers/mt_reg_base.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#define IPC_DSPMBOX_DSP_RSP 0
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#define IPC_DSPMBOX_DSP_REQ 1
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/* 389c9186-5a7d-4ad1-a02c-a02ecdadfb33 */
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DECLARE_SOF_UUID("ipc-task", ipc_task_uuid, 0x389c9186, 0x5a7d, 0x4ad1,
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0xa0, 0x2c, 0xa0, 0x2e, 0xcd, 0xad, 0xfb, 0x33);
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static struct ipc *local_ipc;
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struct ipc_data {
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struct ipc_data_host_buffer dh_buffer;
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};
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static void mbox0_handler(void *args)
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{
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uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(0));
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/* clear interrupt */
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io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(0), op);
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ipc_schedule_process(local_ipc);
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}
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static void mbox1_handler(void *args)
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{
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uint32_t op = io_reg_read(MTK_DSP_MBOX_IN_CMD(1));
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/* clear interrupt */
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io_reg_write(MTK_DSP_MBOX_IN_CMD_CLR(1), op);
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local_ipc->is_notification_pending = false;
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}
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void trigger_irq_to_host_rsp(void)
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{
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io_reg_write(MTK_DSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP);
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}
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void trigger_irq_to_host_req(void)
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{
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io_reg_write(MTK_DSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ);
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}
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enum task_state ipc_platform_do_cmd(void *data)
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{
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ipc_cmd_hdr *hdr;
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hdr = mailbox_validate();
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ipc_cmd(hdr);
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return SOF_TASK_STATE_COMPLETED;
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}
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void ipc_platform_complete_cmd(void *data)
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{
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struct ipc *ipc = data;
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trigger_irq_to_host_rsp();
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while (ipc->pm_prepare_D3)
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wait_for_interrupt(0);
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}
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int ipc_platform_send_msg(struct ipc_msg *msg)
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{
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struct ipc *ipc = ipc_get();
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if (ipc->is_notification_pending)
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return -EBUSY;
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/* now send the message */
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mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
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list_item_del(&msg->list);
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ipc->is_notification_pending = true;
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/* now interrupt host to tell it we have sent a message */
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trigger_irq_to_host_req();
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return 0;
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}
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#if CONFIG_HOST_PTABLE
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struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc)
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{
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struct ipc_data *iipc = ipc_get_drvdata(ipc);
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return &iipc->dh_buffer;
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}
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#endif
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int platform_ipc_init(struct ipc *ipc)
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{
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uint32_t mbox_irq0, mbox_irq1;
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#if CONFIG_HOST_PTABLE
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struct ipc_data *iipc;
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iipc = rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, sizeof(*iipc));
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ipc_set_drvdata(ipc, iipc);
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#else
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ipc_set_drvdata(ipc, NULL);
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#endif
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local_ipc = ipc;
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/* schedule */
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schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), &ipc_task_ops, ipc, 0, 0);
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#if CONFIG_HOST_PTABLE
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/* allocate page table buffer */
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iipc->dh_buffer.page_table =
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rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, PLATFORM_PAGE_TABLE_SIZE);
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iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED);
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if (!iipc->dh_buffer.dmac) {
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tr_err(&ipc_tr, "Unable to find DMA for host page table");
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panic(SOF_IPC_PANIC_IPC);
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}
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#endif
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mbox_irq0 = mtk_get_irq_domain_id(LX_MBOX_IRQ0_B);
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mbox_irq1 = mtk_get_irq_domain_id(LX_MBOX_IRQ1_B);
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interrupt_register(mbox_irq0, mbox0_handler, ipc);
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interrupt_register(mbox_irq1, mbox1_handler, ipc);
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interrupt_enable(mbox_irq0, ipc);
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interrupt_enable(mbox_irq1, ipc);
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return 0;
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}
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@ -0,0 +1,104 @@
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2021 Mediatek
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//
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// Author:Fengquan Chen <fengquan.chen@mediatek.com>
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#include <sof/audio/component_ext.h>
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#include <sof/drivers/interrupt.h>
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#include <sof/lib/memory.h>
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#include <sof/platform.h>
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#include <sof/drivers/timer.h>
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#include <ipc/stream.h>
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#include <errno.h>
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#include <stdint.h>
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void platform_timer_start(struct timer *timer)
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{
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/* nothing to do for cpu timer */
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}
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void platform_timer_stop(struct timer *timer)
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{
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arch_timer_disable(timer);
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}
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int64_t platform_timer_set(struct timer *timer, uint64_t ticks)
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{
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return arch_timer_set(timer, ticks);
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}
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void platform_timer_clear(struct timer *timer)
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{
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arch_timer_clear(timer);
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}
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|
||||
uint64_t platform_timer_get(struct timer *timer)
|
||||
{
|
||||
return arch_timer_get_system(timer);
|
||||
}
|
||||
|
||||
/* IRQs off in arch_timer_get_system() */
|
||||
uint64_t platform_timer_get_atomic(struct timer *timer)
|
||||
{
|
||||
return arch_timer_get_system(timer);
|
||||
}
|
||||
|
||||
/* get timestamp for host stream DMA position */
|
||||
void platform_host_timestamp(struct comp_dev *host,
|
||||
struct sof_ipc_stream_posn *posn)
|
||||
{
|
||||
int err;
|
||||
|
||||
/* get host position */
|
||||
err = comp_position(host, posn);
|
||||
if (err == 0)
|
||||
posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64;
|
||||
}
|
||||
|
||||
/* get timestamp for DAI stream DMA position */
|
||||
void platform_dai_timestamp(struct comp_dev *dai,
|
||||
struct sof_ipc_stream_posn *posn)
|
||||
{
|
||||
int err;
|
||||
|
||||
/* get DAI position */
|
||||
err = comp_position(dai, posn);
|
||||
if (err == 0)
|
||||
posn->flags |= SOF_TIME_DAI_VALID;
|
||||
|
||||
posn->wallclock = timer_get_system(timer_get()) - posn->wallclock;
|
||||
posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64;
|
||||
}
|
||||
|
||||
/* get current wallclock for componnent */
|
||||
void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock)
|
||||
{
|
||||
*wallclock = timer_get_system(timer_get());
|
||||
}
|
||||
|
||||
int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg)
|
||||
{
|
||||
switch (timer->id) {
|
||||
case TIMER0:
|
||||
case TIMER1:
|
||||
return arch_timer_register(timer, handler, arg);
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
void timer_unregister(struct timer *timer, void *arg)
|
||||
{
|
||||
interrupt_unregister(timer->irq, arg);
|
||||
}
|
||||
|
||||
void timer_enable(struct timer *timer, void *arg, int core)
|
||||
{
|
||||
interrupt_enable(timer->irq, arg);
|
||||
}
|
||||
|
||||
void timer_disable(struct timer *timer, void *arg, int core)
|
||||
{
|
||||
interrupt_disable(timer->irq, arg);
|
||||
}
|
||||
Loading…
Reference in New Issue