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rom: linker: cleanup rom linker scripts to use only macros. 

use macros and remove wrong entry point.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood 2018-11-24 16:11:45 +00:00 committed by Liam Girdwood
parent 3c8ac2ac86
commit a9069d680d
7 changed files with 29 additions and 24 deletions
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3
src/platform/apollolake/include/platform/memory.h
View File

@ -378,6 +378,9 @@
#define SOF_MEM_RO_SIZE 0x8 #define SOF_MEM_RO_SIZE 0x8
/* VM ROM sizes */
#define ROM_RESET_TEXT_SIZE 0x400
#define ROM_RESET_LIT_SIZE 0x200
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86

12
src/platform/apollolake/rom.x.in
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@ -16,12 +16,12 @@ MEMORY
{ {
vector_reset_text : vector_reset_text :
org = ROM_BASE, org = ROM_BASE,
len = 0x400 len = ROM_RESET_TEXT_SIZE
vector_reset_lit : vector_reset_lit :
org = ROM_BASE + 0x400, org = ROM_BASE + ROM_RESET_TEXT_SIZE,
len = 0x100 len = ROM_RESET_LIT_SIZE
vector_base_text : vector_base_text :
org = ROM_BASE + 0x800, org = ROM_BASE + ROM_RESET_TEXT_SIZE + ROM_RESET_LIT_SIZE,
len = SOF_MEM_VECBASE_LIT_SIZE len = SOF_MEM_VECBASE_LIT_SIZE
vector_int2_lit : vector_int2_lit :
org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE,
@ -113,12 +113,8 @@ PHDRS
vector_double_text_phdr PT_LOAD; vector_double_text_phdr PT_LOAD;
sof_text_phdr PT_LOAD; sof_text_phdr PT_LOAD;
sof_stack_phdr PT_LOAD; sof_stack_phdr PT_LOAD;
static_log_entries_phdr PT_NOTE;
} }
/* Default entry point: */
ENTRY(_MainEntry)
_rom_store_table = 0; _rom_store_table = 0;
/* ABI0 does not use Window base */ /* ABI0 does not use Window base */

6
src/platform/cannonlake/include/platform/memory.h
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@ -410,6 +410,12 @@
#define SOF_MEM_RESET_LIT_SIZE 0x8 #define SOF_MEM_RESET_LIT_SIZE 0x8
#define SOF_MEM_VECBASE_LIT_SIZE 0x178 #define SOF_MEM_VECBASE_LIT_SIZE 0x178
#define SOF_MEM_RO_SIZE 0x8
/* VM ROM sizes */
#define ROM_RESET_TEXT_SIZE 0x400
#define ROM_RESET_LIT_SIZE 0x200
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000

12
src/platform/cannonlake/rom.x.in
View File

@ -16,12 +16,12 @@ MEMORY
{ {
vector_reset_text : vector_reset_text :
org = ROM_BASE, org = ROM_BASE,
len = 0x400 len = ROM_RESET_TEXT_SIZE
vector_reset_lit : vector_reset_lit :
org = ROM_BASE + 0x400, org = ROM_BASE + ROM_RESET_TEXT_SIZE,
len = 0x100 len = ROM_RESET_LIT_SIZE
vector_base_text : vector_base_text :
org = ROM_BASE + 0x800, org = ROM_BASE + ROM_RESET_TEXT_SIZE + ROM_RESET_LIT_SIZE,
len = SOF_MEM_VECBASE_LIT_SIZE len = SOF_MEM_VECBASE_LIT_SIZE
vector_int2_lit : vector_int2_lit :
org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE,
@ -110,12 +110,8 @@ PHDRS
vector_double_text_phdr PT_LOAD; vector_double_text_phdr PT_LOAD;
sof_text_phdr PT_LOAD; sof_text_phdr PT_LOAD;
sof_stack_phdr PT_LOAD; sof_stack_phdr PT_LOAD;
static_log_entries_phdr PT_NOTE;
} }
/* Default entry point: */
ENTRY(_MainEntry)
_rom_store_table = 0; _rom_store_table = 0;
/* ABI0 does not use Window base */ /* ABI0 does not use Window base */

4
src/platform/icelake/include/platform/memory.h
View File

@ -408,6 +408,10 @@
#define SOF_MEM_RO_SIZE 0x8 #define SOF_MEM_RO_SIZE 0x8
/* VM ROM sizes */
#define ROM_RESET_TEXT_SIZE 0x400
#define ROM_RESET_LIT_SIZE 0x200
/* boot loader in IMR */ /* boot loader in IMR */
#define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
#define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000

12
src/platform/icelake/rom.x.in
View File

@ -16,12 +16,12 @@ MEMORY
{ {
vector_reset_text : vector_reset_text :
org = ROM_BASE, org = ROM_BASE,
len = 0x400 len = ROM_RESET_TEXT_SIZE
vector_reset_lit : vector_reset_lit :
org = ROM_BASE + 0x400, org = ROM_BASE + ROM_RESET_TEXT_SIZE,
len = 0x100 len = ROM_RESET_LIT_SIZE
vector_base_text : vector_base_text :
org = ROM_BASE + 0x800, org = ROM_BASE + ROM_RESET_TEXT_SIZE + ROM_RESET_LIT_SIZE,
len = SOF_MEM_VECBASE_LIT_SIZE len = SOF_MEM_VECBASE_LIT_SIZE
vector_int2_lit : vector_int2_lit :
org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, org = ROM_BASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE,
@ -113,12 +113,8 @@ PHDRS
vector_double_text_phdr PT_LOAD; vector_double_text_phdr PT_LOAD;
sof_text_phdr PT_LOAD; sof_text_phdr PT_LOAD;
sof_stack_phdr PT_LOAD; sof_stack_phdr PT_LOAD;
static_log_entries_phdr PT_NOTE;
} }
/* Default entry point: */
ENTRY(_MainEntry)
_rom_store_table = 0; _rom_store_table = 0;
/* ABI0 does not use Window base */ /* ABI0 does not use Window base */

4
src/platform/suecreek/include/platform/memory.h
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@ -357,6 +357,10 @@
#define SOF_MEM_RO_SIZE 0x8 #define SOF_MEM_RO_SIZE 0x8
/* VM ROM sizes */
#define ROM_RESET_TEXT_SIZE 0x400
#define ROM_RESET_LIT_SIZE 0x200
/* code loader */ /* code loader */
#define BOOT_LDR_TEXT_ENTRY_BASE 0xBE000000 #define BOOT_LDR_TEXT_ENTRY_BASE 0xBE000000
#define BOOT_LDR_TEXT_ENTRY_SIZE 0x400 #define BOOT_LDR_TEXT_ENTRY_SIZE 0x400