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SMP: CNL/WHL/CML prevent power gating on cores 1, 2, 3. 

Prevent ROM from powering off any cores on waiti call.

Signed-off-by: ArturX Kloniecki <arturx.kloniecki@linux.intel.com>
This commit is contained in:
ArturX Kloniecki 2019-02-21 13:55:16 +01:00 committed by Liam Girdwood
parent 73cfb3c92f
commit 9cddf9613d
2 changed files with 4 additions and 2 deletions
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2
src/platform/cannonlake/include/platform/shim.h
View File

@ -194,7 +194,7 @@
#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
#define SHIM_PWRCTL 0x90
#define SHIM_PWRCTL_TCPDSP0PG BIT(0)
#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
#define SHIM_PWRSTS 0x92
#define SHIM_LPSCTL 0x94

4
src/platform/intel/cavs/platform.c
View File

@ -471,7 +471,9 @@ int platform_init(struct sof *sof)
shim_write(SHIM_GPDMA_CLKCTL(1), SHIM_CLKCTL_LPGPDMAFDCGB);
/* prevent DSP Common power gating */
shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSP0PG);
shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSPPG(0) |
SHIM_PWRCTL_TCPDSPPG(1) | SHIM_PWRCTL_TCPDSPPG(2) |
SHIM_PWRCTL_TCPDSPPG(3));
#elif defined(CONFIG_ICELAKE) || defined(CONFIG_SUECREEK)
/* TODO: need to merge as for APL */