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SMP: Fix improper cache invalidation. 

Cache was invalidated in improper order, which led to using rubbish
data on slave core during pipeline trigger start.

Signed-off-by: ArturX Kloniecki <arturx.kloniecki@linux.intel.com>
This commit is contained in:
ArturX Kloniecki 2019-02-21 13:51:05 +01:00 committed by Liam Girdwood
parent 84de2e32c9
commit 73cfb3c92f
1 changed files with 4 additions and 3 deletions
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7
src/audio/pipeline.c
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@ -120,12 +120,13 @@ static int pipeline_for_each_comp(struct comp_dev *current,
/* run this operation further */
list_for_item(clist, buffer_list) {
buffer = buffer_from_list(clist, struct comp_buffer, dir);
buffer_comp = buffer_get_comp(buffer, dir);
/* execute operation on buffer */
if (buff_func)
buff_func(buffer);
buffer_comp = buffer_get_comp(buffer, dir);
/* don't go further if this component is not connected */
if (!buffer_comp)
continue;
@ -364,14 +365,14 @@ static int pipeline_comp_cache(struct comp_dev *current, void *data, int dir)
tracev_pipe("pipeline_comp_cache(), current->comp.id = %u, dir = %u",
current->comp.id, dir);
comp_cache(current, ppl_data->cmd);
if (!comp_is_single_pipeline(current, ppl_data->start)) {
tracev_pipe("pipeline_comp_cache(), "
"current is from another pipeline");
return 0;
}
comp_cache(current, ppl_data->cmd);
return pipeline_for_each_comp(current, &pipeline_comp_cache, data,
comp_buffer_cache_op(ppl_data->cmd),
dir);