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ace: overlay: update clock frequency 

Changing max clock frequency for FPGA configuration.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2023-09-06 16:04:43 +02:00 committed by Daniel Baluta
parent 837f7715f2
commit 5b8ba30694
2 changed files with 2 additions and 0 deletions
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1
app/overlays/lnl/fpga_overlay.conf
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@ -1,2 +1,3 @@
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000 CONFIG_DAI_DMIC_HW_IOCLK=19200000
CONFIG_XTENSA_CCOUNT_HZ=40000000

1
app/overlays/mtl/fpga_overlay.conf
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@ -1,2 +1,3 @@
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000 CONFIG_DAI_DMIC_HW_IOCLK=19200000
CONFIG_XTENSA_CCOUNT_HZ=40000000