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ace: clock: update clock definitions 

ACE_1.5 and ACE_2.0 use only two clocks for DSP cores. First is WOVRCO and
second is ACE IPLL.

IPLL allows to configure it to work like LP RING Oscillator Clock or HP
RING Oscillator Clock. Currently, the driver does not allow this, so I
remove the frequency that cannot be achieved anyway.

Clocks frequencies:
WOV: 38.4 MHz
IPLL: 393.216 MHz

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2023-09-06 15:34:39 +02:00 committed by Daniel Baluta
parent 99c53d90f9
commit 837f7715f2
4 changed files with 12 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/platform/lunarlake/include/platform/lib/clk.h
View File

@ -14,21 +14,19 @@
#include <ace/lib/clk.h>
#define CLK_MAX_CPU_HZ 400000000
#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ
#define CPU_WOVCRO_FREQ_IDX 0
#define CPU_LPRO_FREQ_IDX 1
#define CPU_HPRO_FREQ_IDX 2
#define CPU_IPLL_FREQ_IDX 1
#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX
#define SSP_DEFAULT_IDX 1
#define NUM_CPU_FREQ 3
#define NUM_CPU_FREQ 2
#define NUM_SSP_FREQ 3

5
src/platform/lunarlake/lib/clk.c
View File

@ -9,9 +9,8 @@
#include <rtos/clk.h>
static const struct freq_table platform_cpu_freq[] = {
{ 38400000, 38400 },
{ 120000000, 120000 },
{ CLK_MAX_CPU_HZ, 400000 },
{ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 },
{ CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 },
};
STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);

10
src/platform/meteorlake/include/platform/lib/clk.h
View File

@ -14,21 +14,19 @@
#include <ace/lib/clk.h>
#define CLK_MAX_CPU_HZ 400000000
#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ
#define CPU_WOVCRO_FREQ_IDX 0
#define CPU_LPRO_FREQ_IDX 1
#define CPU_HPRO_FREQ_IDX 2
#define CPU_IPLL_FREQ_IDX 1
#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX
#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX
#define SSP_DEFAULT_IDX 1
#define NUM_CPU_FREQ 3
#define NUM_CPU_FREQ 2
#define NUM_SSP_FREQ 3

5
src/platform/meteorlake/lib/clk.c
View File

@ -9,9 +9,8 @@
#include <rtos/clk.h>
static const struct freq_table platform_cpu_freq[] = {
{ 38400000, 38400 },
{ 120000000, 120000 },
{ CLK_MAX_CPU_HZ, 400000 },
{ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 },
{ CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 },
};
STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);