mirror of https://github.com/thesofproject/sof.git
platform: skl: Add memory map for SKL/KBL platforms
Add memory map and linker script adjustments for SKL and KBL platforms. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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1f5a965711
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@ -9,11 +9,20 @@
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#include <platform/memory.h>
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#include <xtensa/config/core-isa.h>
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#include <config.h>
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OUTPUT_ARCH(xtensa)
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MEMORY
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{
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#if defined(CONFIG_SKYLAKE) || defined(CONFIG_KABYLAKE)
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vector_reset_text :
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org = HP_SRAM_VECBASE_RESET,
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len = HP_SRAM_RESET_TEXT_SIZE
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vector_reset_lit :
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org = HP_SRAM_VECBASE_RESET + HP_SRAM_RESET_TEXT_SIZE,
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len = HP_SRAM_RESET_LIT_SIZE
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#endif
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vector_memory_lit :
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org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE,
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len = SOF_MEM_ERROR_LIT_SIZE
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@ -165,11 +174,13 @@ PHDRS
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}
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/* Default entry point: */
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#if !defined(CONFIG_SKYLAKE) && !defined(CONFIG_KABYLAKE)
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ENTRY(_MainEntry)
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#endif
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_rom_store_table = 0;
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/* ABI0 does not use Window base */
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PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
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PROVIDE(_memmap_vecbase_reset = SOF_MEM_VECBASE);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
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@ -231,6 +242,23 @@ SECTIONS
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_wnd3_end = ABSOLUTE(.);
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} >wnd3 :wnd3_phdr
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#if defined(CONFIG_SKYLAKE) || defined(CONFIG_KABYLAKE)
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.ResetVector.text : ALIGN(4)
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{
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_ResetVector_text_start = ABSOLUTE(.);
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KEEP (*(.ResetVector.text))
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_ResetVector_text_end = ABSOLUTE(.);
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} >vector_reset_text :vector_reset_text_phdr
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.ResetVector.literal : ALIGN(4)
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{
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_ResetVector_literal_start = ABSOLUTE(.);
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*(.ResetVector.literal)
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_ResetVector_literal_end = ABSOLUTE(.);
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} >vector_reset_lit :vector_reset_lit_phdr
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#endif
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.WindowVectors.text : ALIGN(4)
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{
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_WindowVectors_text_start = ABSOLUTE(.);
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@ -215,9 +215,8 @@
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*/
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/* HP SRAM */
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#define SRAM_ALIAS_OFFSET 0x20000000
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#define HP_SRAM_BASE 0xBE000000
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#define HP_SRAM_SIZE 0x00080000
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#define HP_SRAM_MASK 0xFF000000
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/* HP SRAM Heap */
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@ -231,7 +230,7 @@
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/* HP SRAM windows */
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/* window 3 */
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#define SRAM_TRACE_BASE (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
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#define SRAM_TRACE_BASE SRAM_WND_BASE
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#define SRAM_TRACE_SIZE 0x2000
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/* window 2 */
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@ -271,13 +270,45 @@
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#define HP_SRAM_WIN3_BASE SRAM_TRACE_BASE
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#define HP_SRAM_WIN3_SIZE SRAM_TRACE_SIZE
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#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
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/* Apollolake HP-SRAM config */
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#if defined(CONFIG_APOLLOLAKE) \
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&& !(defined(CONFIG_KABYLAKE) || defined(CONFIG_SKYLAKE))
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#define SRAM_ALIAS_OFFSET 0x20000000
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#define HP_SRAM_SIZE 0x00080000
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#define SRAM_WND_BASE (HEAP_HP_BUFFER_BASE + HEAP_HP_BUFFER_SIZE)
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#define HP_SRAM_VECBASE_RESET (HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE)
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#define HP_SRAM_VECBASE_OFFSET 0x0
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#define SOF_TEXT_START (HP_SRAM_VECBASE_RESET + 0x400)
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#define SOF_TEXT_BASE (SOF_TEXT_START)
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#define SOF_TEXT_SIZE (0x1d000 - 0x400)
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/* Skylake or kabylake HP-SRAM config */
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#elif defined(CONFIG_KABYLAKE) || defined(CONFIG_SKYLAKE)
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#define SRAM_ALIAS_OFFSET 0x00000000
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#define HP_SRAM_SIZE 0x0001E0000
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#define SRAM_WND_BASE 0xBE058000
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#define HP_SRAM_VECBASE_RESET 0xBE0A0000
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#define HP_SRAM_VECBASE_OFFSET 0x800
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#define HP_SRAM_RESET_TEXT_SIZE 0x400
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#define HP_SRAM_RESET_LIT_SIZE 0x100
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#define SOF_TEXT_START HP_SRAM_VECBASE_RESET
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#define SOF_TEXT_BASE (SOF_TEXT_START + 0x1000)
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#define SOF_TEXT_SIZE 0x1c000
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#else
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#error Platform not specified
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#endif
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/* initialized data */
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#define SOF_DATA_START (SOF_TEXT_BASE + SOF_TEXT_SIZE)
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#if defined CONFIG_DMIC
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@ -373,7 +404,8 @@
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#define SOF_MEM_ERROR_TEXT_SIZE 0x180
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#define SOF_MEM_ERROR_LIT_SIZE 0x8
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#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET
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#define SOF_MEM_VECBASE \
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(HP_SRAM_VECBASE_RESET + HP_SRAM_VECBASE_OFFSET)
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#define SOF_MEM_VECBASE_LIT_SIZE 0x178
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#define SOF_MEM_RO_SIZE 0x8
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@ -381,8 +413,17 @@
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/* VM ROM sizes */
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#define ROM_RESET_TEXT_SIZE 0x400
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#define ROM_RESET_LIT_SIZE 0x200
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/* boot loader in IMR */
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/* boot loader in IMR - APL uses manifest v1.8 and SKL/KBL use v1.5 */
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#if defined(CONFIG_APOLLOLAKE) \
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&& !(defined(CONFIG_KABYLAKE) || defined(CONFIG_SKYLAKE))
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xB000A000
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#elif defined(CONFIG_KABYLAKE) || defined(CONFIG_SKYLAKE)
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#define IMR_BOOT_LDR_TEXT_ENTRY_BASE 0xBE0A0000
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#else
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#error Platform not specified
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#endif
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#define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x86
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#define IMR_BOOT_LDR_LIT_BASE (IMR_BOOT_LDR_TEXT_ENTRY_BASE + \
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IMR_BOOT_LDR_TEXT_ENTRY_SIZE)
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