OrgACRN
/
sof
mirror of https://github.com/thesofproject/sof.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

lps: make prefctl platfrom specific 

This will allow to enable LPS on TGL

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
This commit is contained in:
Adrian Bonislawski 2020-05-18 16:15:35 +02:00 committed by Liam Girdwood
parent b14e42d48e
commit 136b48cea4
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/platform/cannonlake/include/platform/lib/memory.h
View File

@ -421,6 +421,9 @@
SOF_STACK_TOTAL_SIZE)
#define BOOT_LDR_STACK_SIZE SOF_STACK_TOTAL_SIZE
/* L1 init */
#define L1_CACHE_PREFCTL_VALUE 0x0000
#endif /* __PLATFORM_LIB_MEMORY_H__ */
#else

5
src/platform/intel/cavs/lps_pic_restore_vector.S
View File

@ -8,14 +8,13 @@
#include <xtensa/coreasm.h>
#include <xtensa/cacheattrasm.h>
#include <cavs/lps_ctx.h>
#include <sof/lib/memory.h>
#define MEMCTL_INIT_BIT 23
#define MEMCTL_INIT_VAL (MEMCTL_L0IBUF_EN | 1 << MEMCTL_INIT_BIT)
#define SW_INT_NUM 7
#define SW_INT_MASK (1<<SW_INT_NUM)
#define L1_CACHE_PREFCTL 0x0000
.section .lps_vector, "ax"
lps_pic_restore_vector_literals:
.literal_position
@ -44,7 +43,7 @@ lps_pic_restore_vector:
movi a3, 0x15 /* RCW for non-coherent dcache */
wsr a3, ATOMCTL
movi a2, L1_CACHE_PREFCTL
movi a2, L1_CACHE_PREFCTL_VALUE
wsr a2, PREFCTL
movi a3, PS_UM|PS_WOE