From 136b48cea4d1575f780767128bfcfe77b419acca Mon Sep 17 00:00:00 2001
From: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
Date: Mon, 18 May 2020 16:15:35 +0200
Subject: [PATCH] lps: make prefctl platfrom specific

This will allow to enable LPS on TGL

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@linux.intel.com>
---
 src/platform/cannonlake/include/platform/lib/memory.h | 3 +++
 src/platform/intel/cavs/lps_pic_restore_vector.S      | 5 ++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/platform/cannonlake/include/platform/lib/memory.h b/src/platform/cannonlake/include/platform/lib/memory.h
index 31f8ce838..33829ba87 100644
--- a/src/platform/cannonlake/include/platform/lib/memory.h
+++ b/src/platform/cannonlake/include/platform/lib/memory.h
@@ -421,6 +421,9 @@
 					SOF_STACK_TOTAL_SIZE)
 #define BOOT_LDR_STACK_SIZE		SOF_STACK_TOTAL_SIZE
 
+/* L1 init */
+#define L1_CACHE_PREFCTL_VALUE 0x0000
+
 #endif /* __PLATFORM_LIB_MEMORY_H__ */
 
 #else
diff --git a/src/platform/intel/cavs/lps_pic_restore_vector.S b/src/platform/intel/cavs/lps_pic_restore_vector.S
index b0ac47662..42da750c7 100644
--- a/src/platform/intel/cavs/lps_pic_restore_vector.S
+++ b/src/platform/intel/cavs/lps_pic_restore_vector.S
@@ -8,14 +8,13 @@
 #include <xtensa/coreasm.h>
 #include <xtensa/cacheattrasm.h>
 #include <cavs/lps_ctx.h>
+#include <sof/lib/memory.h>
 
 #define MEMCTL_INIT_BIT 23
 #define MEMCTL_INIT_VAL (MEMCTL_L0IBUF_EN | 1 << MEMCTL_INIT_BIT)
 #define SW_INT_NUM 7
 #define SW_INT_MASK (1<<SW_INT_NUM)
 
-#define L1_CACHE_PREFCTL 0x0000
-
 	.section .lps_vector, "ax"
 lps_pic_restore_vector_literals:
 	.literal_position
@@ -44,7 +43,7 @@ lps_pic_restore_vector:
 	movi    a3, 0x15	/* RCW for non-coherent dcache */
 	wsr     a3, ATOMCTL
 
-	movi a2, L1_CACHE_PREFCTL
+	movi a2, L1_CACHE_PREFCTL_VALUE
 	wsr  a2, PREFCTL
 
 	movi a3, PS_UM|PS_WOE