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ptl: Add FPGA overlay configuration 

Add PTL configuration changes required to build FW
for FPGA. After next SOF rebase default target will be
build for RVP, so for FPGA we will use configuration
overlay.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit is contained in:
Jaroslaw Stelter 2023-05-25 13:16:29 +02:00 committed by Michal Wasko
parent b235797fc0
commit 0f25a31089
1 changed files with 3 additions and 0 deletions
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3
app/overlays/ptl/fpga_overlay.conf Normal file
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
CONFIG_DAI_DMIC_HW_IOCLK=19200000