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apl-ssp: allow for 19.2 MHz SSP reference 

Don't hard-code MCLK source on ApolloLake, use settings provided over
IPC to select 24.576 MHz PLL or 19.2 MHz XTAL oscillator.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
Pierre-Louis Bossart 2018-04-12 21:13:38 -05:00 committed by Liam Girdwood
parent 36f23c6cc3
commit 0cc866fde1
1 changed files with 11 additions and 1 deletions
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12
src/drivers/apl-ssp.c
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@ -479,7 +479,17 @@ static inline int ssp_set_config(struct dai *dai,
#ifdef CONFIG_CANNONLAKE
mdivc = 0x1;
#else
mdivc = 0x00100001;
if (config->ssp.mclk_rate == 24576000) {
/* enable PLL, bypass M/N dividers */
mdivc = 0x00100001;
} else if (config->ssp.mclk_rate == 19200000) {
/* no PLL, use XTAl oscillator as source */
mdivc = 0;
} else {
trace_ssp_error("eci");
ret = -EINVAL;
goto out;
}
#endif
/* bypass divider for MCLK */
mdivr = 0x00000fff;