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Merge pull request #593 from lbetlej/LDOCTL_access_cleanup 

LDO Control - unification of control macros for LDOCTL bits
This commit is contained in:
Liam Girdwood 2018-11-19 14:38:00 +00:00 committed by GitHub
parent 5434ce0f35 c522b6692e
commit 041a56c541
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 39 additions and 36 deletions
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10
src/arch/xtensa/boot_loader.c
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@ -134,12 +134,7 @@ static int32_t hp_sram_init(void)
int delay_count = 256; int delay_count = 256;
uint32_t status; uint32_t status;
#if defined(CONFIG_CANNONLAKE)
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON); shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON);
#else
//TODO: clean up sequence same as for CANNONLAKE
shim_write(SHIM_LDOCTL, SHIM_HPMEM_POWER_ON);
#endif
/* add some delay before touch power register */ /* add some delay before touch power register */
idelay(delay_count); idelay(delay_count);
@ -170,12 +165,7 @@ static int32_t hp_sram_init(void)
/* add some delay before touch power register */ /* add some delay before touch power register */
idelay(delay_count); idelay(delay_count);
#if defined(CONFIG_CANNONLAKE)
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS); shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
#else
//TODO: clean up sequence same as for CANNONLAKE
shim_write(SHIM_LDOCTL, SHIM_LPMEM_POWER_BYPASS);
#endif
return 0; return 0;
} }

16
src/platform/apollolake/include/platform/asm_ldo_management.h
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@ -58,7 +58,7 @@ bnez \ax, 1b
movi \ax, (SHIM_BASE + SHIM_LDOCTL) movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0 l32i \ay, \ax, 0
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK) movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
and \ay, \ax, \ay and \ay, \ax, \ay
or \state, \ay, \state or \state, \ay, \state
@ -69,7 +69,7 @@ m_cavs_set_ldo_state \state, \ax
movi \ax, (SHIM_BASE + SHIM_LDOCTL) movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0 l32i \ay, \ax, 0
// LP SRAM mask // LP SRAM mask
movi \ax, ~(SHIM_LDOCTL_LP_SRAM_MASK) movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
and \ay, \ax, \ay and \ay, \ax, \ay
or \state, \ay, \state or \state, \ay, \state
@ -80,9 +80,9 @@ m_cavs_set_ldo_state \state, \ax
movi \ay, (SHIM_BASE + SHIM_LDOCTL) movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0 l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK) movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \ax, \az and \az, \ax, \az
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_ON | SHIM_LDOCTL_LP_SRAM_LDO_ON) movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
or \ax, \az, \ax or \ax, \az, \ax
m_cavs_set_ldo_state \ax, \ay m_cavs_set_ldo_state \ax, \ay
@ -98,10 +98,10 @@ movi \ax, 128
movi \ay, (SHIM_BASE + SHIM_LDOCTL) movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0 l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK) movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_OFF | SHIM_LDOCTL_LP_SRAM_LDO_OFF) movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
or \ax, \ax, \az or \ax, \ax, \az
s32i \ax, \ay, 0 s32i \ax, \ay, 0
@ -118,10 +118,10 @@ movi \ax, 128
movi \ay, (SHIM_BASE + SHIM_LDOCTL) movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0 l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HP_SRAM_MASK | SHIM_LDOCTL_LP_SRAM_MASK) movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HP_SRAM_LDO_BYPASS | SHIM_LDOCTL_LP_SRAM_LDO_BYPASS) movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
or \ax, \ax, \az or \ax, \ax, \az
s32i \ax, \ay, 0 s32i \ax, \ay, 0

17
src/platform/apollolake/include/platform/shim.h
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@ -222,15 +222,14 @@
/** \brief LDO Control */ /** \brief LDO Control */
#define SHIM_LDOCTL 0xA4 #define SHIM_LDOCTL 0xA4
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
#define SHIM_LDOCTL_HP_SRAM_MASK (3 << 0) #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
#define SHIM_LDOCTL_LP_SRAM_MASK (3 << 2) #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_HP_SRAM_LDO_ON (3 << 0) #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_LP_SRAM_LDO_ON (3 << 2) #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#define SHIM_LDOCTL_HP_SRAM_LDO_BYPASS BIT(0) #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define SHIM_LDOCTL_LP_SRAM_LDO_BYPASS BIT(2) #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
#define SHIM_LDOCTL_HP_SRAM_LDO_OFF (0 << 0) #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
#define SHIM_LDOCTL_LP_SRAM_LDO_OFF (0 << 2)
#define SHIM_HSPGISTS 0xb0 #define SHIM_HSPGISTS 0xb0
#define SHIM_LSPGISTS 0xb4 #define SHIM_LSPGISTS 0xb4

8
src/platform/apollolake/power_down.S
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@ -88,12 +88,12 @@ power_down:
beqz b_enable_lpsram, _PD_DISABLE_HPSRAM beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
_PD_DISABLE_LPSRAM: _PD_DISABLE_LPSRAM:
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_ON movi temp_reg0, SHIM_LDOCTL_LPSRAM_LDO_ON
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2 m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2 m_cavs_lpsram_power_off temp_reg0, temp_reg1, temp_reg2
movi temp_reg0, SHIM_LDOCTL_LP_SRAM_LDO_OFF movi temp_reg0, SHIM_LDOCTL_LPSRAM_LDO_OFF
m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2 m_cavs_set_lpldo_state temp_reg0, temp_reg1, temp_reg2
// DISABLE_HPSRAM is aligned so there can be zeros between // DISABLE_HPSRAM is aligned so there can be zeros between
@ -109,13 +109,13 @@ _PD_DISABLE_HPSRAM:
l32i temp_reg0, pu32_hpsram_mask, 0 l32i temp_reg0, pu32_hpsram_mask, 0
beqz temp_reg0, _PD_SLEEP beqz temp_reg0, _PD_SLEEP
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_ON movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
// Disable L2 cache in case it would be enabled // Disable L2 cache in case it would be enabled
m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2 m_cavs_hpsram_power_off temp_reg0, temp_reg1, temp_reg2
movi temp_reg0, SHIM_LDOCTL_HP_SRAM_LDO_OFF movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF
m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2 m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
// For BXT-P we need to deassert VNN request and select slow XTAL // For BXT-P we need to deassert VNN request and select slow XTAL

2
src/platform/cannonlake/include/platform/shim.h
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@ -205,6 +205,7 @@
#define SHIM_L2_MECS (SHIM_BASE + 0xd0) #define SHIM_L2_MECS (SHIM_BASE + 0xd0)
/** \brief LDO Control */
#define SHIM_LDOCTL 0xA4 #define SHIM_LDOCTL 0xA4
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
@ -215,7 +216,6 @@
#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) #define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) #define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG (1 << 15) #define LPGPDMA_CTLOSEL_FLAG (1 << 15)
#define LPGPDMA_CHOSEL_FLAG (0xFF) #define LPGPDMA_CHOSEL_FLAG (0xFF)

11
src/platform/icelake/include/platform/shim.h
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@ -202,9 +202,16 @@
#define SHIM_L2_MECS (SHIM_BASE + 0xd0) #define SHIM_L2_MECS (SHIM_BASE + 0xd0)
/** \brief LDO Control */
#define SHIM_LDOCTL 0xA4 #define SHIM_LDOCTL 0xA4
#define SHIM_HPMEM_POWER_ON (0x3 << 0) #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0) #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG (1 << 15) #define LPGPDMA_CTLOSEL_FLAG (1 << 15)

11
src/platform/suecreek/include/platform/shim.h
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@ -202,9 +202,16 @@
#define SHIM_L2_MECS (SHIM_BASE + 0xd0) #define SHIM_L2_MECS (SHIM_BASE + 0xd0)
/** \brief LDO Control */
#define SHIM_LDOCTL 0xA4 #define SHIM_LDOCTL 0xA4
#define SHIM_HPMEM_POWER_ON (0x3 << 0) #define SHIM_LDOCTL_HPSRAM_MASK (3 << 0)
#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0) #define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG (1 << 15) #define LPGPDMA_CTLOSEL_FLAG (1 << 15)