2018-09-28 13:02:12 +08:00
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# Topology for SKL+ HDA Generic machine
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#
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2020-09-03 23:49:36 +08:00
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# if XPROC is not defined, define with default pipe
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ifdef(`DMICPROC', , `define(DMICPROC, eq-iir-volume)')
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ifdef(`DMIC16KPROC', , `define(DMIC16KPROC, eq-iir-volume)')
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2021-03-03 00:57:58 +08:00
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ifdef(`HSPROC', , `define(HSPROC, volume)')
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2020-09-03 23:49:36 +08:00
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2018-09-28 13:02:12 +08:00
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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2020-04-02 10:38:37 +08:00
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include(`hda.m4')
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2018-09-28 13:02:12 +08:00
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include bxt DSP configuration
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include(`platform/intel/bxt.m4')
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2019-08-09 07:16:58 +08:00
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# Define pipeline id for intel-generic-dmic.m4
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2019-03-29 10:07:11 +08:00
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# to generate dmic setting
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2019-08-09 07:16:58 +08:00
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ifelse(CHANNELS, `0', ,
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`
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2021-02-12 22:46:54 +08:00
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define(DMIC_PCM_48k_ID, `6')
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define(DMIC_PCM_16k_ID, `7')
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define(DMIC_DAI_LINK_48k_ID, `6')
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define(DMIC_DAI_LINK_16k_ID, `7')
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2019-03-29 10:07:11 +08:00
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define(DMIC_PIPELINE_48k_ID, `10')
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define(DMIC_PIPELINE_16k_ID, `11')
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include(`platform/intel/intel-generic-dmic.m4')
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2019-08-09 07:16:58 +08:00
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'
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)
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2019-03-29 10:07:11 +08:00
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2021-09-11 08:09:47 +08:00
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# The pipeline naming notation is pipe-mixer-PROCESSING-dai-DIRECTION.m4
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2021-01-28 18:12:42 +08:00
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# HSPROC is set by makefile, if not the default above is applied
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2021-09-11 08:09:47 +08:00
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define(PIPE_HEADSET_PLAYBACK, `sof/pipe-mixer-`HSPROC'-dai-playback.m4')
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2020-03-13 13:53:25 +08:00
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2018-09-28 13:02:12 +08:00
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#
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# Define the pipelines
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#
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2019-11-19 19:34:05 +08:00
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# PCM0P --> volume (pipe 1) --> HDA Analog (HDA Analog playback)
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# PCM0C <-- volume, EQ (pipe 2) <-- HDA Analog (HDA Analog capture)
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# PCM1P --> volume (pipe 3) --> HDA Digital (HDA Digital playback)
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# PCM1C <-- volume, EQ (pipe 4) <-- HDA Digital (HDA Digital capture)
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# PCM3 ----> volume (pipe 7) ----> iDisp1 (HDMI/DP playback, BE link 3)
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# PCM4 ----> Volume (pipe 8) ----> iDisp2 (HDMI/DP playback, BE link 4)
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# PCM5 ----> volume (pipe 9) ----> iDisp3 (HDMI/DP playback, BE link 5)
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2018-09-28 13:02:12 +08:00
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#
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2021-01-28 18:12:42 +08:00
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# If HSPROC_FILTERx is defined set PIPELINE_FILTERx
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ifdef(`HSPROC_FILTER1', `define(PIPELINE_FILTER1, HSPROC_FILTER1)', `undefine(`PIPELINE_FILTER1')')
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ifdef(`HSPROC_FILTER2', `define(PIPELINE_FILTER2, HSPROC_FILTER2)', `undefine(`PIPELINE_FILTER2')')
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2018-12-04 16:08:11 +08:00
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# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2019-11-19 19:34:05 +08:00
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PIPELINE_PCM_ADD(sof/pipe-highpass-capture.m4,
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2018-12-04 16:08:11 +08:00
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2, 0, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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2018-12-04 16:08:11 +08:00
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# Low Latency playback pipeline 3 on PCM 1 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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2018-12-04 16:08:11 +08:00
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3, 1, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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2018-12-04 16:08:11 +08:00
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# Low Latency capture pipeline 4 on PCM 1 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2019-11-19 19:34:05 +08:00
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PIPELINE_PCM_ADD(sof/pipe-highpass-capture.m4,
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2018-12-04 16:08:11 +08:00
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4, 1, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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2018-12-04 16:08:11 +08:00
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# Low Latency playback pipeline 7 on PCM 3 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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2018-12-04 16:08:11 +08:00
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7, 3, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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2018-12-04 16:08:11 +08:00
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# Low Latency playback pipeline 8 on PCM 4 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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2018-12-04 16:08:11 +08:00
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8, 4, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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2018-12-04 16:08:11 +08:00
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# Low Latency playback pipeline 9 on PCM 5 using max 2 channels of s24le.
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2021-09-15 20:48:14 +08:00
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# 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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2018-12-04 16:08:11 +08:00
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9, 5, 2, s24le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0,
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48000, 48000, 48000)
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2018-09-28 13:02:12 +08:00
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#
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# DAIs configuration
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#
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# playback DAI is HDA Analog using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2021-09-11 08:09:47 +08:00
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# The 'NOT_USED_IGNORED' is due to dependencies and is adjusted later with an explicit dapm line.
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DAI_ADD(PIPE_HEADSET_PLAYBACK,
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2018-09-28 13:02:12 +08:00
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1, HDA, 0, Analog Playback and Capture,
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2021-09-11 08:09:47 +08:00
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NOT_USED_IGNORED, 2, s32le,
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER, 2, 48000)
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2018-09-28 13:02:12 +08:00
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2021-09-11 08:09:47 +08:00
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# Low Latency playback pipeline 1 on PCM 30 using max 2 channels of s32le.
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2021-09-11 07:57:55 +08:00
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# 1000us deadline on core 0 with priority 0
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2021-09-11 08:09:47 +08:00
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PIPELINE_PCM_ADD(sof/pipe-host-volume-playback.m4,
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30, 0, 2, s32le,
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2021-09-11 07:57:55 +08:00
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1000, 0, 0,
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2021-09-11 08:09:47 +08:00
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48000, 48000, 48000,
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SCHEDULE_TIME_DOMAIN_TIMER,
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PIPELINE_PLAYBACK_SCHED_COMP_1)
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2021-09-11 07:57:55 +08:00
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# Undefine PIPELINE_FILTERx to avoid to propagate elsewhere, other endpoints
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# with filters blobs will need similar handling as HSPROC_FILTERx.
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undefine(`PIPELINE_FILTER1')
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undefine(`PIPELINE_FILTER2')
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2018-09-28 13:02:12 +08:00
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# capture DAI is HDA Analog using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-capture.m4,
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2018-12-04 15:59:38 +08:00
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2, HDA, 1, Analog Playback and Capture,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SINK_2, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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# playback DAI is HDA Digital using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-playback.m4,
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2018-12-04 15:59:38 +08:00
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3, HDA, 2, Digital Playback and Capture,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SOURCE_3, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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# capture DAI is HDA Digital using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-capture.m4,
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2018-12-04 15:59:38 +08:00
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4, HDA, 3, Digital Playback and Capture,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SINK_4, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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# playback DAI is iDisp1 using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-playback.m4,
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2018-12-04 15:59:38 +08:00
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7, HDA, 4, iDisp1,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SOURCE_7, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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# playback DAI is iDisp2 using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-playback.m4,
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2018-12-04 15:59:38 +08:00
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8, HDA, 5, iDisp2,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SOURCE_8, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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# playback DAI is iDisp3 using 2 periods
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2021-09-15 20:48:14 +08:00
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# Dai buffers use s32le format, 1000us deadline with priority 0 on core 0
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2018-09-28 13:02:12 +08:00
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DAI_ADD(sof/pipe-dai-playback.m4,
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2018-12-04 15:59:38 +08:00
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9, HDA, 6, iDisp3,
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2019-01-25 16:12:03 +08:00
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PIPELINE_SOURCE_9, 2, s32le,
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2019-01-03 20:11:21 +08:00
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1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
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2018-09-28 13:02:12 +08:00
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2021-09-11 08:09:47 +08:00
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SectionGraph."mixer-host" {
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index "0"
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lines [
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# connect mixer dai pipelines to PCM pipelines
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dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_30)
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]
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}
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PCM_DUPLEX_ADD(HDA Analog, 0, PIPELINE_PCM_30, PIPELINE_PCM_2)
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2018-09-28 13:02:12 +08:00
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PCM_DUPLEX_ADD(HDA Digital, 1, PIPELINE_PCM_3, PIPELINE_PCM_4)
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PCM_PLAYBACK_ADD(HDMI1, 3, PIPELINE_PCM_7)
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PCM_PLAYBACK_ADD(HDMI2, 4, PIPELINE_PCM_8)
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PCM_PLAYBACK_ADD(HDMI3, 5, PIPELINE_PCM_9)
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#
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# BE configurations - overrides config in ACPI if present
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#
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# HDA outputs
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2020-04-02 10:38:37 +08:00
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DAI_CONFIG(HDA, 0, 4, Analog Playback and Capture,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 0, 48000, 2)))
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DAI_CONFIG(HDA, 1, 5, Digital Playback and Capture,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 1, 48000, 2)))
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2018-09-28 13:02:12 +08:00
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# 3 HDMI/DP outputs (ID: 3,4,5)
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2020-04-02 10:38:37 +08:00
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DAI_CONFIG(HDA, 4, 1, iDisp1,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 4, 48000, 2)))
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DAI_CONFIG(HDA, 5, 2, iDisp2,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 5, 48000, 2)))
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DAI_CONFIG(HDA, 6, 3, iDisp3,
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HDA_CONFIG(HDA_CONFIG_DATA(HDA, 6, 48000, 2)))
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2018-09-28 13:02:12 +08:00
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2018-09-29 10:22:30 +08:00
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2018-12-04 15:59:38 +08:00
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VIRTUAL_DAPM_ROUTE_IN(codec0_in, HDA, 1, IN, 1)
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VIRTUAL_DAPM_ROUTE_IN(codec1_in, HDA, 3, IN, 2)
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2018-09-29 10:22:30 +08:00
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VIRTUAL_DAPM_ROUTE_OUT(codec0_out, HDA, 0, OUT, 3)
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2018-12-04 15:59:38 +08:00
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VIRTUAL_DAPM_ROUTE_OUT(codec1_out, HDA, 2, OUT, 4)
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2018-09-29 10:22:30 +08:00
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# codec2 is not supported in dai links but it exists
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# in dapm routes, so hack this one to HDA1
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2018-12-04 15:59:38 +08:00
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VIRTUAL_DAPM_ROUTE_IN(codec2_in, HDA, 3, IN, 5)
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VIRTUAL_DAPM_ROUTE_OUT(codec2_out, HDA, 2, OUT, 6)
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2018-09-29 10:22:30 +08:00
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2018-12-04 15:59:38 +08:00
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VIRTUAL_DAPM_ROUTE_OUT(iDisp1_out, HDA, 4, OUT, 7)
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VIRTUAL_DAPM_ROUTE_OUT(iDisp2_out, HDA, 5, OUT, 8)
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VIRTUAL_DAPM_ROUTE_OUT(iDisp3_out, HDA, 6, OUT, 9)
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2019-05-04 02:55:37 +08:00
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VIRTUAL_WIDGET(iDisp3 Tx, out_drv, 0)
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VIRTUAL_WIDGET(iDisp2 Tx, out_drv, 1)
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VIRTUAL_WIDGET(iDisp1 Tx, out_drv, 2)
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VIRTUAL_WIDGET(Analog CPU Playback, out_drv, 3)
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VIRTUAL_WIDGET(Digital CPU Playback, out_drv, 4)
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VIRTUAL_WIDGET(Alt Analog CPU Playback, out_drv, 5)
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2019-05-08 14:39:03 +08:00
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VIRTUAL_WIDGET(Analog CPU Capture, input, 6)
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VIRTUAL_WIDGET(Digital CPU Capture, input, 7)
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VIRTUAL_WIDGET(Alt Analog CPU Capture, input, 8)
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