sof/west.yml

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---
# SOF west manifest
manifest:
version: "0.13"
defaults:
remote: thesofproject
remotes:
- name: thesofproject
url-base: https://github.com/thesofproject
- name: zephyrproject
url-base: https://github.com/zephyrproject-rtos
# When upgrading projects here please run git log --oneline in the
# project and if not too long then include the output in your commit
# message. See examples of good commit messages at
# https://github.com/thesofproject/sof/commits/4e1d3ba61abd3/rimage
# (git log 4e1d3ba61abd3 -- rimage/)
# WARNING: for backwards compatibility with non-Zephyr platforms,
# rimage and toml99 are STILL git submodules! Every time you change
# their `revision` revision here you MUST keep their git submodules in
# sync. This is as simple as `git add rimage` before committing (+
# `git commit --amend` if you forgot and already committed this
# west manifest file).
# When a submodule is out of sync then both `git status` and `git
# describe` notice and a "-dirty" suffix appears in the SOF version.
# It is generally very bad practice to git push without looking
# at "git status"; even without submodules.
# rimage and tomlc99 to Zephyr's west manifest discussion:
# https://github.com/zephyrproject-rtos/zephyr/issues/58212
projects:
- name: rimage
repo-path: rimage
path: sof/rimage
revision: 4fb9fe00575bc2e9f14570803d811987fb27f010
- name: tomlc99
repo-path: tomlc99
path: sof/rimage/tomlc99
revision: e3a03f5ec7d8d33be705c5ce8a632d998ce9b4d1
- name: zephyr
repo-path: zephyr
west.yml: update Zephyr to 5689916a70ad Contains 450+ commits, including following directly affecting SOF targets: 5689916a70ad soc: xtensa: intel_adsp: cavs: fix assert on L3_MEM_BASE_ADDR 34ea488da91c intel_adsp: ace20_lnl: add ALH DAI support b7e181c2708b soc: intel_adsp: add HDA buffer interrupt functions d68a58d6cd26 dts: xtensa: intel: add HDA DMA interrupt defs for ACE2.0 62c7729b3e1a dts: xtensa: intel: add HDA DMA interrupt defs for cAVS platforms c6c6c5a5ed64 soc: intel_adsp: ace shim: add force L1 defines 0fead68e2b8e Revert "llvm: use proper syntax for --config option" cd97eae73b4b soc: xtensa: intel_adsp: common: s/device.h/init.h 6cdabb4dff5e soc: xtensa: intel_adsp: common: add missing section_tags.h c360284c6e14 soc: xtensa: intel_adsp: add missing init.h ffd2121c65d3 soc: xtensa: intel_adsp: cavs: fix power_down_cavs() signature a1d7ffdc374d soc: xtensa: intel_adsp: cavs: fix incorrect cached/uncached cast ce7c30c12978 soc: intel_adsp/ace: use WAIT_FOR for core power transitions 3f0ee7f6db7a power_domain: intel_adsp: initialize after DMA ca23a5f0cf75 xtensa: mmu: allow SoC to do additional MMU init steps 088a31e2bffa xtensa: mmu: preload ITLB for VECBASE before restoring... 40f2486b685c xtensa: mmu: rename MMU_KERNEL_RING to Z_XTENSA_KERNEL_RING... 18eb17f4cd69 xtensa: mmu: add arch_reserved_pages_update 4778c13bbeab xtensa: mmu: handle all data TLB misses in double exception c723d8b8d3ac xtensa: Add missing synchronization 24148718fc6e xtensa: mmu: cache common data and heap if !XTENSA_RPO_CACHE b6ccbae58dc4 xtensa: mmu: use _image_ram_start/end for data region 257404a14327 xtensa: mmu: init: only clear enough entries in way 6 614e64325d48 xtensa: mmu: no longer identity map the first 512MB b5016714b082 xtensa: mmu: handle TLB misses during user exception 98ffd1addd6a xtensa: crt1: call z_xtensa_mmu_init 38d4b7872401 xtensa: mmu: remove printing vaddr registers during exception 3d63e2060edf dts: cpu: add cdns,tensilica-xtensa-lx3 Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2023-08-30 19:12:09 +08:00
revision: 5689916a70ad5c363bd7d5511b772ada90067d51
remote: zephyrproject
# Import some projects listed in zephyr/west.yml@revision
#
# Warning: changes to zephyr/west.yml or to any other _imported_
# west.yml file are _ignored_ by design! Only the above
# 'revision:' of zephyr/west.yml is used.
import:
name-whitelist:
- hal_xtensa
- hal_nxp
- mbedtls
- mipi-sys-t
- lz4
- tinycrypt
self:
# Changes to submanifests/*.yml files _are_ effective; these have no
# specified 'revision:'
import: submanifests