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sof/app/boards/intel_adsp_cavs25.conf

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zephyr: app: move main SOF app from zephyr samples Make the main SOF app part of SOF, where it belongs. No need for any overlays (which just duplicated the sample .conf anyways) and one place to build everything. This now does not depend on zephyr samples, which have a different purpose completely. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 10:22:07 +08:00
CONFIG_TIGERLAKE=y
CONFIG_INTEL_DMIC=y
tgl: hda: enable chain dma Enable building chain dma component on TGL platform Signed-off-by: Piotr Makaruk <piotr.makaruk@intel.com>
2022-11-29 20:35:46 +08:00
CONFIG_COMP_CHAIN_DMA=y
intel: drivers: dmic refactor - move DMIC_HW_IOCLK to Kconfig Moved hardcoded cycles values for DMIC IO from dmic.h header to per-platform configuration file (defconfig files for non-Zephyr builds and app/boards for Zephyr builds). Added new entry to intel drivers Kconfig - CONFIG_DMIC_HW_IOCLK. Modification of this clock value may be used for testing purposes like building firmware for FPGA or simulator. Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-08-16 08:35:22 +08:00
CONFIG_DMIC_HW_IOCLK=38400000
zephyr: app: move main SOF app from zephyr samples Make the main SOF app part of SOF, where it belongs. No need for any overlays (which just duplicated the sample .conf anyways) and one place to build everything. This now does not depend on zephyr samples, which have a different purpose completely. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-13 10:22:07 +08:00
CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=30
CONFIG_RIMAGE_SIGNING_SCHEMA="tgl"