mirror of https://github.com/thesofproject/sof.git
intel: drivers: dmic refactor - move DMIC_HW_IOCLK to Kconfig
Moved hardcoded cycles values for DMIC IO from dmic.h header to per-platform configuration file (defconfig files for non-Zephyr builds and app/boards for Zephyr builds). Added new entry to intel drivers Kconfig - CONFIG_DMIC_HW_IOCLK. Modification of this clock value may be used for testing purposes like building firmware for FPGA or simulator. Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
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@ -1,5 +1,6 @@
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CONFIG_APOLLOLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=19200000
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CONFIG_INTEL_SSP=y
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CONFIG_LP_MEMORY_BANKS=2
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CONFIG_HP_MEMORY_BANKS=8
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@ -1,5 +1,6 @@
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CONFIG_CANNONLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=24000000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_ICELAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_ICELAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_LP_MEMORY_BANKS=1
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CONFIG_HP_MEMORY_BANKS=16
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@ -1,5 +1,6 @@
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CONFIG_TIGERLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_TIGERLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_APOLLOLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=19200000
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CONFIG_INTEL_SSP=y
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CONFIG_CORE_COUNT=1
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CONFIG_LP_MEMORY_BANKS=2
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@ -1,5 +1,6 @@
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CONFIG_CANNONLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=24000000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_CANNONLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=24000000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_CAVS_LPS=y
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@ -1,5 +1,6 @@
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CONFIG_ICELAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,6 +1,7 @@
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CONFIG_ICELAKE=y
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CONFIG_RIMAGE_SIGNING_SCHEMA="jsl"
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_CORE_COUNT=2
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CONFIG_LP_MEMORY_BANKS=1
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@ -1,5 +1,6 @@
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CONFIG_SUECREEK=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=19200000
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CONFIG_INTEL_SSP=y
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CONFIG_LP_MEMORY_BANKS=1
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CONFIG_HP_MEMORY_BANKS=47
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@ -1,5 +1,6 @@
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CONFIG_SUECREEK=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=19200000
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CONFIG_INTEL_SSP=y
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CONFIG_LP_MEMORY_BANKS=1
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CONFIG_HP_MEMORY_BANKS=47
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@ -1,6 +1,7 @@
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CONFIG_TIGERLAKE=y
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CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h"
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_CORE_COUNT=2
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CONFIG_TIGERLAKE=y
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CONFIG_INTEL_DMIC=y
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CONFIG_DMIC_HW_IOCLK=38400000
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CONFIG_INTEL_SSP=y
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CONFIG_INTEL_ALH=y
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CONFIG_LP_MEMORY_BANKS=1
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@ -52,6 +52,13 @@ config INTEL_DMIC
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if INTEL_DMIC
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config DMIC_HW_IOCLK
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int "Set DMIC hw IO clock"
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default 0
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help
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Hardware specific DMIC IO clock speed defined by each platform.
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May be overridden from hardware values for simulation purposes.
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choice
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prompt "Driver operation mode"
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default INTEL_DMIC_TPLG_PARAMS
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@ -102,7 +102,7 @@ int timestamp_dmic_config(struct dai *dai, struct timestamp_cfg *cfg)
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return -EINVAL;
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}
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cfg->walclk_rate = DMIC_HW_IOCLK;
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cfg->walclk_rate = CONFIG_DMIC_HW_IOCLK;
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return 0;
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}
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@ -67,7 +67,7 @@ static void find_modes(struct dai *dai,
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/* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
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if (dmic->global->prm[di].pdmclk_max < DMIC_HW_PDM_CLK_MIN ||
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dmic->global->prm[di].pdmclk_max > DMIC_HW_IOCLK / 2) {
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dmic->global->prm[di].pdmclk_max > CONFIG_DMIC_HW_IOCLK / 2) {
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dai_err(dai, "find_modes(): pdm clock max not in range");
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return;
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}
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}
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/* Min and max clock dividers */
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clkdiv_min = ceil_divide(DMIC_HW_IOCLK, dmic->global->prm[di].pdmclk_max);
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clkdiv_min = ceil_divide(CONFIG_DMIC_HW_IOCLK, dmic->global->prm[di].pdmclk_max);
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clkdiv_min = MAX(clkdiv_min, DMIC_HW_CIC_DECIM_MIN);
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clkdiv_max = DMIC_HW_IOCLK / dmic->global->prm[di].pdmclk_min;
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clkdiv_max = CONFIG_DMIC_HW_IOCLK / dmic->global->prm[di].pdmclk_min;
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/* Loop possible clock dividers and check based on resulting
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* oversampling ratio that CIC and FIR decimation ratios are
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du_max = 100 - du_min;
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/* Calculate PDM clock rate and oversampling ratio. */
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pdmclk = DMIC_HW_IOCLK / clkdiv;
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pdmclk = CONFIG_DMIC_HW_IOCLK / clkdiv;
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osr = pdmclk / fs;
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/* Check that OSR constraints is met and clock duty cycle does
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mcic = osr / mfir;
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ioclk_test = fs * mfir * mcic * clkdiv;
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if (ioclk_test == DMIC_HW_IOCLK &&
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if (ioclk_test == CONFIG_DMIC_HW_IOCLK &&
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mcic >= DMIC_HW_CIC_DECIM_MIN &&
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mcic <= DMIC_HW_CIC_DECIM_MAX &&
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i < DMIC_MAX_MODES) {
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if (mfir <= 0)
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return fir;
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cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
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cic_fs = CONFIG_DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
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fs = cic_fs / mfir;
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/* FIR max. length depends on available cycles and coef RAM
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* length. Exceeding this length sets HW overrun status and
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* overwrite of other register.
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*/
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fir_max_length = MIN(DMIC_HW_FIR_LENGTH_MAX,
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DMIC_HW_IOCLK / fs / 2 -
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CONFIG_DMIC_HW_IOCLK / fs / 2 -
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DMIC_FIR_PIPELINE_OVERHEAD);
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i = 0;
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@ -567,7 +567,7 @@ int dmic_set_config_nhlt(struct dai *dai, void *spec_config)
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return -EINVAL;
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}
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dmic->dai_rate = DMIC_HW_IOCLK / rate_div;
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dmic->dai_rate = CONFIG_DMIC_HW_IOCLK / rate_div;
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dai_info(dai, "dmic_set_config_nhlt(): rate = %d, channels = %d, format = %d",
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dmic->dai_rate, dmic->dai_channels, dmic->dai_format);
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return 0;
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@ -38,28 +38,24 @@
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#if CONFIG_APOLLOLAKE
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#define DMIC_HW_VERSION 1
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#define DMIC_HW_CONTROLLERS 2
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#define DMIC_HW_IOCLK 19200000
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#define DMIC_HW_FIFOS 2
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#endif
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#if CONFIG_CANNONLAKE
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#define DMIC_HW_VERSION 1
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#define DMIC_HW_CONTROLLERS 2
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#define DMIC_HW_IOCLK 24000000
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#define DMIC_HW_FIFOS 2
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#endif
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#if CONFIG_SUECREEK
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#define DMIC_HW_VERSION 2
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#define DMIC_HW_CONTROLLERS 4
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#define DMIC_HW_IOCLK 19200000
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#define DMIC_HW_FIFOS 2
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#endif
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#if CONFIG_ICELAKE || CONFIG_TIGERLAKE
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#define DMIC_HW_VERSION 1
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#define DMIC_HW_CONTROLLERS 2
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#define DMIC_HW_IOCLK 38400000
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#define DMIC_HW_FIFOS 2
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#endif
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