158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
/** @file
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PCI command register operations supporting functions implementation for PCI Bus module.
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Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/PciExpressLib.h>
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#include "InternalPciEnumerationLib.h"
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/**
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Check the capability supporting by given device.
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@param[in] PciIoDevice Pointer to instance of PCI_IO_DEVICE.
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@retval TRUE Capability supported.
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@retval FALSE Capability not supported.
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**/
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BOOLEAN
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PciCapabilitySupport (
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IN PCI_IO_DEVICE *PciIoDevice
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)
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{
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if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Locate capability register block per capability ID.
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@param[in] PciIoDevice A pointer to the PCI_IO_DEVICE.
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@param[in] CapId The capability ID.
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@param[in, out] Offset A pointer to the offset returned.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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**/
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EFI_STATUS
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LocateCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT8 CapId,
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IN OUT UINT8 *Offset
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)
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{
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UINT8 CapabilityPtr;
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UINT16 CapabilityEntry;
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UINT8 CapabilityID;
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//
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// To check the capability of this device supports
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//
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if (!PciCapabilitySupport (PciIoDevice)) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
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CapabilityPtr = PciExpressRead8 (PciIoDevice->Address + EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR);
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} else {
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CapabilityPtr = PciExpressRead8 (PciIoDevice->Address + PCI_CAPBILITY_POINTER_OFFSET);
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}
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}
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while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
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CapabilityEntry = PciExpressRead16 (PciIoDevice->Address + CapabilityPtr);
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CapabilityID = (UINT8) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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return EFI_SUCCESS;
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}
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//
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// Certain PCI device may incorrectly have capability pointing to itself,
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// break to avoid dead loop.
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//
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if (CapabilityPtr == (UINT8) (CapabilityEntry >> 8)) {
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break;
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}
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CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
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}
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return EFI_NOT_FOUND;
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}
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/**
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Locate PciExpress capability register block per capability ID.
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@param[in] PciIoDevice A pointer to the PCI_IO_DEVICE.
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@param[in] CapId The capability ID.
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@param[in, out] Offset A pointer to the offset returned.
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@retval EFI_SUCCESS Successfully located capability register block.
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@retval EFI_UNSUPPORTED Pci device does not support capability.
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@retval EFI_NOT_FOUND Pci device support but can not find register block.
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**/
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EFI_STATUS
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LocatePciExpressCapabilityRegBlock (
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IN PCI_IO_DEVICE *PciIoDevice,
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IN UINT16 CapId,
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IN OUT UINT32 *Offset
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)
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{
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UINT32 CapabilityPtr;
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UINT32 CapabilityEntry;
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UINT16 CapabilityID;
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//
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// To check the capability of this device supports
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//
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if (!PciIoDevice->IsPciExp) {
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return EFI_UNSUPPORTED;
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}
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if (*Offset != 0) {
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CapabilityPtr = *Offset;
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} else {
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CapabilityPtr = EFI_PCIE_CAPABILITY_BASE_OFFSET;
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}
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while (CapabilityPtr != 0) {
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//
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// Mask it to DWORD alignment per PCI spec
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//
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CapabilityPtr &= 0xFFC;
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CapabilityEntry = PciExpressRead32 (PciIoDevice->Address + CapabilityPtr);
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if (CapabilityEntry == MAX_UINT32) {
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DEBUG ((DEBUG_WARN, "PCI Address 0x08X failed to access at offset 0x%X\n",
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PciIoDevice->Address, CapabilityPtr));
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break;
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}
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CapabilityID = (UINT16) CapabilityEntry;
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if (CapabilityID == CapId) {
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*Offset = CapabilityPtr;
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return EFI_SUCCESS;
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}
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CapabilityPtr = (CapabilityEntry >> 20) & 0xFFF;
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}
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return EFI_NOT_FOUND;
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}
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