2d7c2b920f
In 64-bit operation, some PCI devices have high mmio BARs, but 32-bit FSP can only access 32-bit memory space. This introduces and additional PCI resource downgrade option to downgrade all PCI devices under Bus-0. - self._PCI_ENUM_DOWNGRADE_BUS0 = 1 Force to have 32-bit BAR for all Bus-0 devices Signed-off-by: Aiden Park <aiden.park@intel.com> |
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InternalPciEnumerationLib.c | ||
InternalPciEnumerationLib.h | ||
PciAri.c | ||
PciAri.h | ||
PciCommand.c | ||
PciCommand.h | ||
PciEnumerationLib.c | ||
PciEnumerationLib.inf | ||
PciIov.c | ||
PciIov.h |