56 lines
2.0 KiB
C
56 lines
2.0 KiB
C
/** @file
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Register names for PCIE standard register
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_REGS_H_
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#define _PCIE_REGS_H_
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#include <IndustryStandard/Pci30.h>
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#define R_PCI_BAR0_OFFSET 0x10
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//
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// L1 Sub-States Extended Capability Register (CAPID:001Eh)
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//
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#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on value
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#define N_PCIE_EX_L1SCAP_PTV 19
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#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on scale
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#define N_PCIE_EX_L1SCAP_PTPOS 16
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#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mode Restore time
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#define N_PCIE_EX_L1SCAP_CMRT 8
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#define V_PCIE_EX_L1SCAP_PTPOS_2us 0
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#define V_PCIE_EX_L1SCAP_PTPOS_10us 1
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#define V_PCIE_EX_L1SCAP_PTPOS_100us 2
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#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
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#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
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#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
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#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 supported
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#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 supported
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//
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// PTM Extended Capability Register (CAPID:001Fh)
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//
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#define B_PCIE_EX_PTMCAP_PTMRC BIT2 ///< PTM Root Capable
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#define B_PCIE_EX_PTMCAP_PTMRSPC BIT1 ///< PTM Responder Capable
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//
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// Base Address Offset
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//
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#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
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#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
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#endif
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