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slimbootloader/Silicon/ElkhartlakePkg/Include/PcieRegs.h

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Use LF line endings in the repository Convert the line endings stored for all text files in the repository to LF. The majority previously used DOS-style CRLF line endings. Add a .gitattributes file to enforce this and treat certain extensions as never being text files. Update PatchCheck.py to insist on LF line endings rather than CRLF. However, its other checks fail on this commit due to lots of pre-existing complaints that it only notices because the line endings have changed. Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch needs to be treated as binary since it contains a mixture of line endings. This change has implications depending on the client platform you are using the repository from: * Windows The usual configuration for Git on Windows means that text files will be checked out to the work tree with DOS-style CRLF line endings. If that's not the case then you can configure Git to do so for the entire machine with: git config --global core.autocrlf true or for just the repository with: git config core.autocrlf true Line endings will be normalised to LF when they are committed to the repository. If you commit a text file with only LF line endings then it will be converted to CRLF line endings in your work tree. * Linux, MacOS and other Unices The usual configuration for Git on such platforms is to check files out of the repository with LF line endings. This is probably the right thing for you. In the unlikely even that you are using Git on Unix but editing or compiling on Windows for some reason then you may need to tweak your configuration to force the use of CRLF line endings as described above. * General For more information see https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings . Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400 Signed-off-by: Mike Crowe <mac@mcrowe.com>
2021-11-10 19:36:23 +08:00
/** @file
Register names for PCIE standard register
Conventions:
- Prefixes:
Definitions beginning with "R_" are registers
Definitions beginning with "B_" are bits within registers
Definitions beginning with "V_" are meaningful values within the bits
Definitions beginning with "S_" are register sizes
Definitions beginning with "N_" are the bit position
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCIE_REGS_H_
#define _PCIE_REGS_H_
#include <IndustryStandard/Pci30.h>
#define R_PCI_BAR0_OFFSET 0x10
//
// L1 Sub-States Extended Capability Register (CAPID:001Eh)
//
#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on value
#define N_PCIE_EX_L1SCAP_PTV 19
#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on scale
#define N_PCIE_EX_L1SCAP_PTPOS 16
#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mode Restore time
#define N_PCIE_EX_L1SCAP_CMRT 8
#define V_PCIE_EX_L1SCAP_PTPOS_2us 0
#define V_PCIE_EX_L1SCAP_PTPOS_10us 1
#define V_PCIE_EX_L1SCAP_PTPOS_100us 2
#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 supported
#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 supported
//
// PTM Extended Capability Register (CAPID:001Fh)
//
#define B_PCIE_EX_PTMCAP_PTMRC BIT2 ///< PTM Root Capable
#define B_PCIE_EX_PTMCAP_PTMRSPC BIT1 ///< PTM Responder Capable
//
// Base Address Offset
//
#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
#endif