483 lines
25 KiB
Python
483 lines
25 KiB
Python
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2021 - 2024, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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import time
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import *
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_RPLS'
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 4
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
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self.BOARD_NAME = 'rpls'
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self.BOARD_PKG_NAME = 'AlderlakeBoardPkg'
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self.SILICON_PKG_NAME = 'AlderlakePkg'
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self.BOARD_PKG_NAME_OVERRIDE = 'RaptorlakeBoardPkg'
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self.FSP_IMAGE_ID = 'ADLI-FSP'
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self._EXTRA_INC_PATH = ['Silicon/RaptorlakePkg/Rpls/Fsp']
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self._FSP_PATH_NAME = 'Silicon/RaptorlakePkg/Rpls/Fsp'
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self.FSP_INF_FILE = 'Silicon/RaptorlakePkg/Rpls/Fsp/FspBinRpls.inf'
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self.MICROCODE_INF_FILE = 'Silicon/RaptorlakePkg/Rpls/Microcode/MicrocodeRpls.inf'
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self.ACPI_TABLE_INF_FILE = 'Platform/AlderlakeBoardPkg/AcpiTables/AcpiTablesRpl.inf'
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self.PCI_EXPRESS_BASE = 0xC0000000
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self.PCI_IO_BASE = 0x00002000
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self.PCI_MEM32_BASE = 0x80000000
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self.ACPI_PM_TIMER_BASE = 0x1808
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self.FLASH_LAYOUT_START = 0x100000000 # 4GB Top
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self.FLASH_BASE_SIZE = 0x02000000 # 32MB
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self.FLASH_BASE_ADDRESS = (self.FLASH_LAYOUT_START - self.FLASH_BASE_SIZE)
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self.LOADER_ACPI_RECLAIM_MEM_SIZE = 0x000090000
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self.HAVE_FIT_TABLE = 1
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self.HAVE_VBT_BIN = 1 # TBD
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 1
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self.HAVE_FLASH_MAP = 1
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self.HAVE_ACPI_TABLE = 1
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_SPLASH = 1
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.ENABLE_VTD = 1
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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self.ENABLE_SOURCE_DEBUG = 0
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# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
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self.SKIP_STAGE1A_SOURCE_DEBUG = 1
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self.ENABLE_PCIE_PM = 1
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# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
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self.ENABLE_SMM_REBASE = 2
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0xFF
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self.ENABLE_MULTI_USB_BOOT_DEV = 1
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self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 32
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if self.HAVE_FIT_TABLE:
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self.FIT_ENTRY_MAX_NUM = 17
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# RSA2048 or RSA3072
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self._RSA_SIGN_TYPE = 'RSA3072'
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# 'SHA2_256' or 'SHA2_384'
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self._SIGN_HASH = 'SHA2_384'
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# 0x01 for SHA2_256 or 0x02 for SHA2_384
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self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
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# 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
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self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK['SHA2_384'] | IPP_CRYPTO_ALG_MASK['SHA2_256']
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# G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
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self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI'] | IPP_CRYPTO_OPTIMIZATION_MASK['SHA384_W7']
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# Key configuration
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self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
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self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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self.ENABLE_SMP_INIT = 1 # SMP is N/A on SIMICS
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self.ENABLE_FWU = 1
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self.ENABLE_SMBIOS = 1
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self.ENABLE_CSME_UPDATE = 1
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# CSME update library is required to enable this option and will be available as part of CSME kit
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self.BUILD_CSME_UPDATE_DRIVER = 0
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self.STAGE1A_XIP = 1
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self.STAGE1B_XIP = 1
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self.STAGE2_XIP = 0
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self.STAGE1A_SIZE = 0x0001B000
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x00014000
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self.FSP_M_STACK_TOP = 0xFEF7FF00
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self.STAGE1B_SIZE = 0x00200000
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self.STAGE2_SIZE = 0x000CD000
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x001F0000
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self.PAYLOAD_SIZE = 0x00032000
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self.EPAYLOAD_SIZE = 0x00230000
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self.OS_LOADER_FD_SIZE = 0x00059000
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self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
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self.ENABLE_FAST_BOOT = 0
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try:
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if os.environ['SBL_ENABLE_FAST_BOOT'] == '1':
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self.ENABLE_FAST_BOOT = 1
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except Exception:
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pass
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if self.ENABLE_FAST_BOOT:
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self.ENABLE_SPLASH = 0
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self.ENABLE_FRAMEBUFFER_INIT = 0
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self.RELEASE_MODE = 1
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self.HAVE_VERIFIED_BOOT = 0
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self.HAVE_MEASURED_BOOT = 0
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self.VERIFIED_BOOT_HASH_MASK = 0
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self.HAVE_PSD_TABLE = 0
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if self.RELEASE_MODE and self.ENABLE_FAST_BOOT:
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self.STAGE1A_SIZE = 0x00016000
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self.STAGE1B_SIZE = 0x000D0000
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self.STAGE2_SIZE = 0x000C0000
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self.STAGE2_FD_SIZE = 0x000F0000
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self.PAYLOAD_SIZE = 0x00024000
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if self.ENABLE_SOURCE_DEBUG:
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self.STAGE1B_SIZE += 0x4000
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if self.SKIP_STAGE1A_SOURCE_DEBUG == 0:
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self.STAGE1A_SIZE += 0x4000
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self.UEFI_VARIABLE_SIZE = 0x1000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.UEFI_VARIABLE_SIZE = 0x00040000
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self.UCODE_SIZE = 0x000D8000
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self.MRCDATA_SIZE = 0x00010000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.VARIABLE_SIZE = 0x00002000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
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self.TOP_SWAP_SIZE = 0x00080000
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self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
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self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
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self.SIIPFW_SIZE = 0x1000
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# Declaring UCODE_SLOT_SIZE populates the uCode region with as many
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# uCode slots as possible, even if there aren't enough uCode patches
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# to fill each slot. This can have a slight performance impact on SBL,
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# as it tries to load dummy uCode patches.
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self.UCODE_SLOT_SIZE = 0x48000
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# If ENABLE_SBL_RESILIENCY is 1, BiosRedAssistance FIT strap setting
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# needs to be manually changed to Enabled and TopSwapOverride
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# flash setting needs to be manually changed to 4MB in stitch config
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self.ENABLE_SBL_RESILIENCY = 0
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self.BUILD_IDENTICAL_TS = 0
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if self.ENABLE_SBL_RESILIENCY:
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self.BUILD_IDENTICAL_TS = 1
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if self.BUILD_IDENTICAL_TS:
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self.TOP_SWAP_SIZE = 0x400000
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self.REDUNDANT_SIZE = self.STAGE2_SIZE + self.FWUPDATE_SIZE + self.CFGDATA_SIZE + \
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self.KEYHASH_SIZE
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else:
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self.TOP_SWAP_SIZE = 0x80000
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self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
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self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
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self.ENABLE_TCC = 0
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self.ENABLE_TSN = 0
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if self.ENABLE_TSN:
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self.TMAC_SIZE = 0x00001000
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self.SIIPFW_SIZE += self.TMAC_SIZE
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self.NON_REDUNDANT_SIZE = 0x3BF000 + self.SIIPFW_SIZE
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self.NON_VOLATILE_SIZE = 0x001000
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self.SLIMBOOTLOADER_SIZE = (self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 + \
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self.NON_REDUNDANT_SIZE + self.NON_VOLATILE_SIZE
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self.SLIMBOOTLOADER_SIZE = ((self.SLIMBOOTLOADER_SIZE + 0xFFFFF) & ~0xFFFFF)
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self.PLD_HEAP_SIZE = 0x04000000
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self.PLD_STACK_SIZE = 0x00020000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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self.KM_SIZE = 0x00000400
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self.BPM_SIZE = 0x00000600
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self.ACM_SIZE = 0x00040000 + self.KM_SIZE + self.BPM_SIZE
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# adjust ACM_SIZE to meet 256KB alignment (to align 256KB ACM size)
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if self.ACM_SIZE > 0:
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acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
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acm_btm = acm_top - self.ACM_SIZE
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acm_btm = (acm_btm & 0xFFFC0000)
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self.ACM_SIZE = acm_top - acm_btm
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self.LOADER_RSVD_MEM_SIZE = 0xC00000
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# If mulitple VBT table support is required, list them as:
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# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
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# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
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# the ImageId field in the VBT container.
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# VbtFileName is the VBT file name. It needs to be located under platform
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# VbtBin folder.
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self._MULTI_VBT_FILE = {1:'Vbt_rpls.dat'}
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
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self._generated_cfg_file_prefix = 'Autogen_'
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self._CFGDATA_INT_FILE = []
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self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgDataInt_Rpls_Rvp_Ddr5.dlt', self._generated_cfg_file_prefix + 'CfgDataInt_Rpls_Rvp_SODdr5.dlt']
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def PlatformBuildHook (self, build, phase):
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if phase == 'pre-build:before':
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# create build folder if not exist
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if not os.path.exists(build._fv_dir):
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os.makedirs(build._fv_dir)
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# Generate the dlt files based on feature
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brd_cfg_src_dir = os.path.join(os.environ['SBL_SOURCE'], 'Platform', self.BOARD_PKG_NAME, 'CfgData')
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brd_cfg2_src_dir = '.'
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if hasattr(self, 'BOARD_PKG_NAME_OVERRIDE'):
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brd_cfg2_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME_OVERRIDE, 'CfgData')
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for dlt_file in self._CFGDATA_EXT_FILE:
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cfg_dlt_file = os.path.join(brd_cfg_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
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if not os.path.exists(cfg_dlt_file):
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cfg_dlt_file = os.path.join(brd_cfg2_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
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lines = open (cfg_dlt_file).read()
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# Enable TSN in dlt file
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if self.ENABLE_TSN:
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if os.path.exists(os.path.join(brd_cfg_src_dir, 'CfgData_Tsn_Feature.dlt')):
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lines += open (os.path.join(brd_cfg_src_dir, 'CfgData_Tsn_Feature.dlt')).read()
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else:
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lines += open (os.path.join(brd_cfg2_src_dir, 'CfgData_Tsn_Feature.dlt')).read()
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# Write to generated final dlt file
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output_cfg_dlt_file = os.path.join(build._fv_dir, dlt_file)
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open(output_cfg_dlt_file, 'w').write(lines)
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def GetPlatformDsc (self, BuildPkgName = "BootLoaderCorePkg"):
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dsc = {}
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# These libraries will be added into the DSC files
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = [
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'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
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'SerialPortLib|BootloaderCommonPkg/Library/SerialPortLib/SerialPortLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'ResetSystemLib|Platform/$(BOARD_PKG_NAME)/Library/ResetSystemLib/ResetSystemLib.inf',
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'GpioLib|Silicon/CommonSocPkg/Library/GpioLib/GpioLib.inf',
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'GpioSiLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioSiLib/GpioSiLib.inf',
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'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
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'TccLib|Silicon/CommonSocPkg/Library/TccLib/TccLib.inf',
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'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
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'FspmUpdUpdateLib|Platform/$(BOARD_PKG_NAME_OVERRIDE)/Library/FspmUpdUpdateLib/FspmUpdUpdateLib.inf',
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'FspsUpdUpdateLib|Platform/$(BOARD_PKG_NAME_OVERRIDE)/Library/FspsUpdUpdateLib/FspsUpdUpdateLib.inf',
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'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
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'PchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
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'PchPcrLib|Silicon/CommonSocPkg/Library/PchPcrLib/PchPcrLib.inf',
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'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
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'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
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'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
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'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
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'SmbusLib|Silicon/CommonSocPkg/Library/SmbusLib/SmbusLib.inf',
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'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
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'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
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'MeChipsetLib|Silicon/$(SILICON_PKG_NAME)/Library/MeChipsetLib/MeChipsetLib.inf',
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'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
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'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
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'HeciMeExtLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciMeExtLib/HeciMeExtLib.inf',
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'MeExtMeasurementLib|Silicon/$(SILICON_PKG_NAME)/Library/MeExtMeasurementLib/MeExtMeasurementLib.inf',
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'CpuPcieHsPhyInitLib|Silicon/$(SILICON_PKG_NAME)/Library/CpuPcieHsPhyInitLib/CpuPcieHsPhyInitLib.inf',
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'WatchDogTimerLib|Silicon/CommonSocPkg/Library/WatchDogTimerLib/WatchDogTimerLib.inf',
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'TcoTimerLib|Silicon/CommonSocPkg/Library/TcoTimerLib/TcoTimerLib.inf',
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'TopSwapLib|Silicon/CommonSocPkg/Library/TopSwapLib/TopSwapLib.inf'
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]
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if self.BUILD_CSME_UPDATE_DRIVER:
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
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if self.ENABLE_PCIE_PM:
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lib = [
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'PciePm|Silicon/$(SILICON_PKG_NAME)/Library/PciePm/PciePm.inf',
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'PciExpressHelpersLib|Silicon/$(SILICON_PKG_NAME)/Library/PciExpressHelpersLibrary/PciExpressHelpersLibrary.inf',
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'BasePcieHelperLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePcieHelperLib/BasePcieHelperLib.inf',
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'PcieClientRpLib|Silicon/$(SILICON_PKG_NAME)/Library/PcieClientRpLib/PcieClientRpLib.inf',
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'BasePchPciBdfLib|Silicon/$(SILICON_PKG_NAME)/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf',
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]
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].extend (lib)
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else:
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dsc['LibraryClasses.%s' % self.BUILD_ARCH].append ('PciePm|Silicon/CommonSocPkg/Library/PciePmNull/PciePmNull.inf')
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dsc['PcdsFixedAtBuild'] = ['gPlatformModuleTokenSpaceGuid.PcdAcpiTablesMaxEntry | 40']
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return dsc
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying container header
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HASH_USAGE['PUBKEY_CONT_DEF'],
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'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Use RSA2048 key for verifying OS image signed with RSA2048
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC_RSA2048'
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),
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(
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# Use RSA3072 key for verifying OS image signed with RSA3072
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC_RSA3072'
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),
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]
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return pub_key_list
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def GetContainerList (self):
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container_list = []
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container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
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container_list.append (
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# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
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# ========================================================================================================================================================
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('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0 , 0), # Container Header
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)
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bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
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if self.ENABLE_TSN:
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TsnSubRegion = os.path.join(bins, 'TsnSubRegion.bin')if os.path.exists(os.path.join(bins, 'TsnSubRegion.bin')) else ''
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container_list.append (
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('TMAC',TsnSubRegion, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TMAC_SIZE, 0), # TSN MAC Address
|
|
)
|
|
|
|
return [container_list]
|
|
|
|
def GetOutputImages (self):
|
|
# define extra images that will be copied to output folder
|
|
img_list = ['SlimBootloader.txt',
|
|
'FlashMap.txt',
|
|
'CfgDataStitch.py',
|
|
'CfgDataDef.yaml']
|
|
return img_list
|
|
|
|
def GetImageLayout (self):
|
|
img_list = []
|
|
|
|
acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
|
|
fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
|
|
cfg_flag = 0 if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS else STITCH_OPS.MODE_FILE_IGNOR
|
|
|
|
if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.PLATFORMDATA:
|
|
img_list.extend ([
|
|
('CFGDATA_PDR.bin', [
|
|
('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
])
|
|
|
|
img_list.extend ([
|
|
('NON_VOLATILE.bin', [
|
|
('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('NON_REDUNDANT.bin', [
|
|
('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('EPAYLOAD.bin', '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('PAYLOAD.bin' , 'Lz4' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
])
|
|
|
|
if self.BUILD_IDENTICAL_TS:
|
|
img_list.extend ([
|
|
('REDUNDANT_A.bin', [
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('REDUNDANT_B.bin', [
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_A.bin', [
|
|
('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_B.bin', [
|
|
('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
])
|
|
else:
|
|
img_list.extend ([
|
|
('REDUNDANT_A.bin', [
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('REDUNDANT_B.bin', [
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_A.bin', [
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_B.bin', [
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
])
|
|
|
|
img_list.extend ([
|
|
('SlimBootloader.bin', [
|
|
('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
]
|
|
),
|
|
])
|
|
|
|
return img_list
|