FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
This commit fixes two AHCI operations:
1. AhciWriteBlocks: caused by wrong command
2. AhciGetMediaInfo: caused by wrong offset
The patches also updates the EFI_ATA_IDENTIFY_DATA to align with the ATA8-ACS.
In addition, this commit ports the following changes from EDK2, to enhance the
command completion and trace:
1. cc28ab7a1d7: MdeModulePkg/AtaAtapiPassThru: Check IS to check for command completion
2. b465a811006: MdeModulePkg/AtaAtapiPassThru: Add SATA error recovery flow
3. 64e25d4b062: MdeModulePkg/AtaAtapiPassThru: Restart failed packets
4. 91d95113d07: MdeModulePkg/AtaAtapiPassThru: Trace ATA packets
5. 4c7ce0d285b: MdeModulePkg AtaAtapiPassThru: Skip the potential NULL pointer access
Last, the commit adjusts OS_LOADER_FD_SIZE for several platforms for x64 build
Verified: Using BlockIoTest to test with SATA SSD disk on TGL-UP3
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Increase the size of the UEFI payload container to accommodate increased
payload size from Edk2 network driver and UNDI driver.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPLS] Update RPLS to align with MR1 release
Instead of sharing config data, RPL-S used full config data
from RaptorlakeBoardPkg. With this change, it updated its
default boot option (removed TCC binary) without impacting
other platforms. And in its default config data, it doesn't
need include SPD data for other platforms.
Will update FSP and Microcode separately once they are available.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [RPLS] Update to use MR1 FSP
Update SBL to use MR1 FSP
Signed-off-by: Guo Dong <guo.dong@intel.com>
---------
Signed-off-by: Guo Dong <guo.dong@intel.com>
ADL groups GPIO pins into different sets for different PCH series.
The current CfgData uses ADLS's GPIO group sets as the base, and
overwrites the GrpIdx fields via DLT files for other PCH series.
This results in two issues:
1. "CfgDataTool.py export" command failed to extract DLT files
from SBL image, since it cannot identify the proper group
index in CfgDataExt.bin from the base table in CfgDataInt.bin
2. When using ConfigEditor.py to configure the PadGroup field of
GPIO Payload Selection, it will map to a wrong group index.
This patch separates CfgDataDef.yaml for each of PCH series
- add _CFGDATA_DEF_FILE in BoardConfig.py
- add board extension yaml files for Adln, Adlp, Adls
* CfgDataDef*.yaml
* CfgData_Gpio_*.yaml
* CfgData_PayloadSelection_*.yaml
- assign an invalid/unique GrpIdx for the unused GPIO group
* e.g. 1F, 1E, ..
- adjust GrpIdx of CfgDataExt_Upx12.dlt based on Adlp
- revise the payload selection information in DLT files
This patch also fixes the issue:
- When ConfigEditor opens CfgDataDef.yaml more than once, the
config changes will not be caught by "Save Config Changes to
Delta File"
It is because the "info" argument of build_cfg_list() in
GenCfgData.py will retain its value in the lifetime of
ConfigEditor, and the offset will overflow. So need to reset
the offset for a fresh load_yaml().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Removed GopConfigLib and GopConfig header files
SBL will skip the runtime VBT update and will only consume updated VBT
SBL only pass the VBT reference to FSP without perform update
The updated VBTs for all platform boards will stored in VbtBin folder
Signed-off-by: Kobe <kok.tong.ong@intel.com>
Randy