Commit Graph

1660 Commits

Author SHA1 Message Date
Kevin Tsai eb98e8b8aa Add board name to clean command
1.Build script will not copy FSP, VBT and Microcode bin files from repository
  if it finds these files existing in taget folders.
  Above step keeps them from unintentional update in series of build process.
  Adding a board name to clean command helps to get latest binaries from repository
  in next build.

2.Ignore empty board name from loading BoardConfig*.py

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-05-04 20:53:08 -07:00
Sean McGinn f9d614c09f Move MB/ACPI macros to BootloaderCommonLib
Move macros to BootloaderCommonLib as they
are now consumed by both SBL stages and payload

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Sean McGinn f4d890a479 Remove unnecessary packages/includes from OsLoader
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Sean McGinn 39403a81e7 Remove S3 resume condition on OsLoader TPM event logging
Since OsLoader will never be exercised on S3 resume, there
is no need to check if boot mode is S3 resume before logging
TPM events in OsLoader

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Sean McGinn 43e8103df3 [ADL] Extend IPFW hashes into TPM PCRs
This change extends IPFW hashes into TPM PCRs
as all FW is supposed to have its hash in TPM PCRs

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Sean McGinn 23fafd59b8 Standardize conditions in which hashes get extended to TPM PCRs
This change ensures that consistent APIs are called to
determine if a hash gets extended to TPM PCRs

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-05-04 13:25:07 -07:00
Vincent Chen 6453595afb fix: correct the error handling for ApplyFwImage() in FirmwareUpdate.c
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2023-05-04 13:23:00 -07:00
Randy ccfa918d24 feat: Support HDMI audio playback on EHL
Test config on CRB:
  Set PchHdaEnable=1 in CfgData_GpuConfig.yaml
  Linux OS, test by speaker-test -c 2 -D hw:0,7

Signed-off-by: Randy <randy.lin@intel.com>
2023-05-03 09:17:05 -07:00
bejeanmo 50db060f7a
fix: [RPL-P] CRB hang in UEFI payload when PCIe switch present. (#1892)
This change only sets the GFX framebuffer cache type to Write-combining
when not booting the UEFI payload. The UEFI payload PCI hostbridge driver
will override the WC setting anways for the whole PCI root bridge memory
range, so it wasn't gaining the write-combining performance bonus, and was
causing a CPU exception in this particular case for RPL-P.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-05-03 09:20:58 -04:00
Barnes 084fa47f78 [RPL-S] Updated automation file to include RPL-S
upstream RPL-S and added the build of RPL-S to
automation

Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
2023-05-01 07:40:29 -07:00
Barnes 125bdd597e [RPL-S] Upstream RPL-S
Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
2023-04-28 11:15:20 -07:00
Barnes ccc98a136c [ALL Platforms] Update Build tools impact all
platforms

Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file

Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
2023-04-27 10:20:32 -07:00
Barnes d8822031d9 [ALL Platforms] Update Build tools impact all
platforms

Update Build scripts to take a different file path and Name
for
-- microcode_inf_file
-- fsp_inf_file

Signed-off-by: Barnes <kimberly.d.barnes@intel.com>
2023-04-27 10:20:32 -07:00
Bejean Mosher 96f72c39b8 feat: FuSa Configuration library template, and ADL/RPL FuSa Cfg Data.
Added Null template for FusaConfigLib. Platforms supporting FuSa should
follow this template for enabling FuSa configuration prior to FSP-M and
FSP-S.

Added ADL/RPL CfgData fields for FuSa according to SBL FuSa software
requirements, and dlt file for enabling FuSa and related configuration.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-04-26 14:54:21 -07:00
Kevin Tsai ab2bfd39e2 [UPX i12] Initialize GPIO configurations
Program GPIO settings matching BIOS.
Skip GPIO pins that cause boot issue.

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-04-26 14:48:28 -07:00
sean-m-mcginn 598f12347f
[ADL] Additional TPM-related cleanup (#1881)
Update copyright years
Initialize pointers to NULL
Check pointers for NULL before de-reference
Standardize debug logs

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-04-26 11:39:22 -07:00
sean-m-mcginn ba9da25442
[ADL] Update TPM event logging to match BIOS (#1859)
* [ADL] Update TPM event logging to match BIOS

If measured boot disabled via BtG profile but enabled via SBL
config flag, skip logging startup locality TPM event

If measured boot enabled via BtG profile or SBL config flag, log
CRTM version TPM event

Set startup locality based off startup locality on ACM policy status

Log detail and authority PCR events based off SCTRM status on ACM
policy status

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

* Initialize startup locality and remove measured boot check

Initialize startup locality variable used in setting up event
log

Remove measured boot check as it is not seen in BIOS and it
occurs at higher level

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>

---------

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-04-20 16:37:18 -07:00
Guo Dong bd36df5fa7 feat: (ADL/RPL) Config FSP post code via Port80 or I2C
Add config data for FSP post code

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-04-19 09:25:26 -07:00
Sindhura Grandhi 01f2b130f8 feat: [ADLP/ADLPS] Add pre-commit checks for ADL SKUs
- Adding pre-commit checks for the missing ADL SKUs.
- Resolve build issues

Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
2023-04-18 16:02:17 -07:00
randylintw 08afb8cf23
fix: [ADL-PS] Fix for TSN build error caused by FSP UPD updates. (#1872)
FSP M-UPD was updated so PchTsnEnable is now a 2-byte array with a
separate byte for each port.

Signed-off-by: Randy <randy.lin@intel.com>
2023-04-18 11:20:36 -04:00
Guo Dong d087b7d21d feat: (RPL) Add Crash log data PCD
Define PCD PcdCrashLogDataPtr for Crash log.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-04-14 11:17:56 -07:00
Aakash Panwar 834a01351f feat: Added support to set ref_clock frequency for UFS device
This Patch add the support to set UFS clock frequency.
- Added the function to read or write specified attribute of a UFS device
- Shifted function which switch the link power mode and gear after ref_clock setting
  because if an unsuported clock frequency being set, it won't be able to overwrite
  the corrupted UFS attributes.

Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-04-13 20:35:20 -07:00
Sean McGinn 3b994258d6 Show error code as hex on CSME update failure
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-04-12 22:59:23 -07:00
Sean McGinn 0a62b06e22 Align CSME update with BIOS/driver
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-04-12 22:59:23 -07:00
Bejean Mosher 72cb5df4ab feat: [ADL/RPL] Update CrashLog support implementation for latest FSP.
New CrashLog support design is for FSP to collect CrashLog info and report
in HOB. Bootloader responsibility is just to populate ACPI BERT with FSP
collected CrashLog Data now. That way bootloader has no Silicon code.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-04-12 15:49:52 -07:00
Vincent Chen a3d3c59588 [ADLP] Update FSP/platform version for MR3 release
- update FSP version to IoT ADL-P MR3 (0C.01.75.10)
- update platform version to 1.3

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2023-04-12 15:46:40 -07:00
Guo Dong 42492ffea9 feat: Fix the HelloWorld build failure
When building HelloWorld, it would build failure since SBL core
package is missing in PayloadPkg.dsc since
In general, the payload should not depend on BootloaderCorePkg.
Currently PcdAcpiEnabled is used in the payload entry module and
it is defined in the BootloaderCorePkg. This patch updates the
code to remove the dependency.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-04-11 11:05:29 -07:00
Ionut Nechita a7b6f8adb4
fix: variable is not named correctly (#1865)
Description:
 - GetVaraibelStoreBase to GetVariableStoreBase

Change-Id: I79ddb319d733ebb53131f0df6143bd18bb9aaee7

Signed-off-by: Ionut Nechita <ionut_n2001@yahoo.com>
2023-04-11 09:29:10 -07:00
Sindhura Grandhi 8066b297b3
[ADL/RPL] Add MMC option for OS loader (#1861)
ADL boards come with emmc as an in-built boot media.
Add EMMC option in the default list in order for the OS to boot
up when using OS loader payload.

Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
2023-04-10 14:19:57 -04:00
Bejean Mosher 1186dc0712 fix: [ADL/RPL] SBL image larger than 16MB hangs after TempRamInit.
The PCH decodes MMIO accesses to the top of 4GB to SPI flash for a maximum
window size of 16MB. For SBL images larger than 16MB, this PostTempRamInit
hook was causing the MTRR to overlap with NEM stack set up by FSP-T,
causing a hang.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-04-03 15:18:12 -07:00
tsaikevin 801334666a
[UPX i12] Enable UPX i12 basic boot (#1857)
Add support for Up Xtreme i12 ADLP based board.
The PCIe M.2 slot CN12 on the board is able to detect NVMe SSD.
Debug output is enabled at header CN9 on the board(e.g. UART1)
Tested to boot with OS loader payload and UEFI payload.

To stitch the SlimBootloader.bin with IFWI uses StitchLoader.py script with '-p' as given below:

python Platform/AlderlakeBoardPkg/Script/StitchLoader.py -i <BIOS_IMAGE_NAME> -s Outputs/adlp/SlimBootloader.bin -o sbl_upx12_ifwi.bin -p 0xAA000104

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-04-03 18:03:21 -04:00
Vincent Chen 155d6cc427 fix: verify fwupdate capsule only when Verified Boot is enabled
Firmware update got failed when verified boot was turned off.
While fwupdate capsule is always generated with signing key,
it should be verified only when verified boot is enabled.
Otherwise, raise a warning to inform that the capsule is not
authenticated.

Signed-off-by: Vincent Chen <vincent.chen@intel.com>
2023-03-28 15:55:26 -07:00
Sean McGinn 04e872d77b Remove unnecessary continue statement in TPM library
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-28 15:55:01 -07:00
Sean McGinn b8830af723 Enhance TPM2 Logs
Show error message whenever an unsupported PCR bank is used

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-28 15:55:01 -07:00
Sean McGinn e207c062d9 Change SecureBootPolicy TPM Event Type
Whenever EV_EFI_VARIABLE_DRIVER_CONFIG is specified as TPM event type,
the data that accompanies it is expected to be an UEFI variable in the
appropriate format

This change fixes an erroneously typed TPM event so that the tpm2_eventlog
command works in Linux

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-28 15:55:01 -07:00
Sean McGinn ca7c2796d1 Change Event Type and PCR Number for Extending Config Data into TPM PCR
Align event type and PCR number with BIOS implementation

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-28 15:55:01 -07:00
Guo Dong ba7e1e6924
[ADL/RPL] Add the missing type for SBL config data (#1852)
The type for SBL config MrcSafeConfig is missing.
Missing type will cause this item is not shown
from ConfigEditor tool.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-03-28 08:23:47 -04:00
koktong-ong c7fbc86eb3
Added FspNonVolatileStorageHob2 support in FspSupportLib (#1850)
Support FSP 2.3 FSP_NON_VOLATILE_STORAGE_HOB2

Signed-off-by: Kobe <kok.tong.ong@intel.com>
2023-03-24 08:33:10 -04:00
Atharva Lele 5e48d930f9
fix: Generate FlashMap.txt before Stitch_Components.zip is created (#1853)
Currently, FlashMap.txt is generated *after* the output files are copied.
This results in FlashMap.txt being missing from the output folder on a
clean build. On subsequent rebuilds, the FlashMap.txt is from the previous
build so any layout changes are not reflected.

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-03-23 08:17:58 -04:00
Randy 1bd9f03d34 [EHL] Update FSP and platform version since MR6 is released
- update FSP version to MR6 (09.04.51.31)
- update platform version to 1.6
Verify on EHL CRB.

Signed-off-by: Randy Lin <randy.lin@intel.com>
2023-03-22 10:50:24 -07:00
Guo Dong 39ee698960
[ADL/RPL] Update PlatformMemorySize default value (#1847)
SBL config data PlatformMemorySize is used to set FSP UPD
PlatformMemorySize which is used by FSP to check available
memory range size for FSP reserved memory.
A too small size might cause FSP to use a small available
memory range used for other purpose. So change the default
value of PlatformMemorySize to 64MB.
Since default value change, remove unnecessary override.

Signed-off-by: Guo Dong <guo.dong@intel.com>
2023-03-20 15:10:41 -04:00
Sindhura Grandhi da12add993 [ADL] Remove BIOS region protection overrides
BIOS region has been protected at an earlier place in this file
based on the boot mode. Removing these hard-coded values
as these override the previous behavior. Tested with UEFI payload
and see no boot issues.

Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
2023-03-17 08:31:22 -07:00
Stanley Chang 8b68d1033a code cleanup - PchCycleDecodingLib
remove commented-out functions from PchCycleDecodingLib

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2023-03-14 16:05:23 -07:00
Atharva Lele 1c807e51fa
Fix OsLoader handling of non-container images and remove PcdContainerBootEnabled (#1843)
* OsLoader: set default status to EFI_UNSUPPORTED when parsing a boot image

This was set to EFI_SUCCESS which resulted in ParseBootImages() returning
EFI_SUCCESS even if the boot image was not a container or a component.

Thus, the boot would continue and fail at a later stage due to the
LoadedImage structure not being populated correctly.

Setting it to EFI_UNSUPPORTED will result in ParseBootImages() returning
EFI_UNSUPPORTED if a non-supported boot image is provided and OsLoader
will attempt to boot the next entry in the boot options list.

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

* Remove PcdContainerBootEnabled PCD

SBL requires boot images to be packaged as a container or a component

Signed-off-by: Atharva Lele <atharva.lele@intel.com>

---------

Signed-off-by: Atharva Lele <atharva.lele@intel.com>
2023-03-10 14:14:13 -08:00
cshur c993c5faec [ICX-D] Update StitchScript for new IGFW
Ignition fw requires new parameter for IRC.
(In Ignition FW MR2 V E5.05.00.04.96.0)

Signed-off-by: cshur <cs.hur@intel.com>
2023-03-07 14:20:02 -07:00
Bejean Mosher 2c81ff2e71 fix: [RPL-P] Build error when ENABLE_SOURCE_DEBUG=1.
On platforms where only serial console input is enabled, enabling
source debug will lead to an infinite loop in ConsoleRead(). Newer
compilers detect this and generate a build error.

Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
2023-03-07 14:16:13 -07:00
tsaikevin a9a4328890 [ADLN] Upstream ADLN
This patch open source ADLN project to be able to build
and stitch PV release from open source repo.

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
2023-03-07 14:11:45 -07:00
cshur f0b13a0941
[ICXD][LCC] Update Microcode for both LCC and HCC (#1839)
Version update 1.1 to 1.2.
Update Microcode 201 to 230

Signed-off-by: cshur <cs.hur@intel.com>
2023-03-07 11:30:47 -07:00
Sean McGinn f3d515cd32 Cast FW blob pointers to UINTN then UINT64
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-06 10:48:47 -07:00
Sean McGinn 0c4dca2a82 Log the correct TPM2 event type for stage hashing
In BIOS, all stage measurements are of type
EV_EFI_PLATFORM_FIRMWARE_BLOB. This change aligns SBL
with BIOS.

Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-03-06 10:48:47 -07:00