This patch reworked the previous reverted commit. The UEFI payload
debug version assertion was resolved. Checked in Windows, the SMBIOS
info looks good.
Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This records the maximum usage of heap at runtime. The Stage1/2 heap
sometimes reaches OUT OF RESOURCE even if it looks there is enough
usable space in the heap. This is because AllocateTemporaryMemory()
sometime exceeds the heap boundary. ex) IppCryptoLib
This would help identify proper heap size required in each stages.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This reverts commit b87d67c1fc.
In the testing, it caused debug UEFI payload assertion issue.
Roll it back for now.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current UEFI payload showed 0 KB RAM size in setup screen because
of missing SMBIOS memory type information. This patch added SMBIOS
type 19 to provide memory array mapped address information. With
this change, UEFI setup screen can show correct memory size.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On TGL platform, when enable SR_IOV for PCI enumeration, system
hung due to insufficient PCI resource. GFX VF needs lots of MMIO
resource and it cannot be satisfied by SBL in 32 bit mode.
To address this issue, this patch extends the bus 0 downgrade
policy to further allow downgrading PCI bus 0 devices except for
GFX. Now the DowngradeBus0 policy has following values:
0: Do not downgrade PCI devices on bus 0
1: Downgrade all PCI devices on bus 0
2: Downgrade all PCI devices on bus 0 but GFX
3: Reserved
By default, it has the same behavior as before. If platform needs
to download bus 0 devices but GFX, the new value 2 can be used.
This has been tested on TGL, and it worked as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled ELF UEFI Universal Payload boot for SBL. It was
tested with EDK2 commit 22873f58c40c496d59a0553bee1c720192ac35c9.
To build UEFI Universal Payload, please run script from EDK2 repo:
edksetup.bat
python UefiPayloadPkg\UniversalPayloadBuild.py -b DEBUG -t VS2019
The generated payload binary will be located at:
Build\UefiPayloadPkgX64\UniversalPayload.elf
This patch was tested on QEMU, and it worked as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PciBus lib expects the root bridge resource base should not be
greater than limit. It is true for normal case. However, to mark the
source is unavailable, the base could be less than the limit in some
case. PCI bus lib should only validate the resource that does have a
request.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This adds additional APIs to make Platform code use APIs to access
LoaderGlobalData instead of accessing variables directly.
- GetS3DataPtr()
- SetFeatureCfg()
- ClearFspHob()
- GetVerInfoPtr()
Signed-off-by: Aiden Park <aiden.park@intel.com>
Some platforms need TempRam Base & Size information to calculate
FspmArchUpd StackBase & Size at runtime.
The TempRam Base & Size info will be only valid until TempRamExit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch clears RTC Alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
This patch also refactors RegRead/RegWrite in RestoreS3RegInfo
to avoid the misalingment of function pointers and coding
convention.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Currently it will return a valid SMMBASE_INFO if SMMBASE_INFO_COMM_ID
is found in SMM S3 resume memory. It will cause issue in S3 path if there
is no one fill correct data when MpInit uses it to rebase SMM.
This patch adds a check to SMMBASE_INFO to avoid this issue.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
- fix __aullshr link error due to compiler intrinsics functions
for NOOPT build in Windows
- adjust Stage1A/TopSwap/OsLoader FD size for NOOPT target
- adjust Stage2 size for NOOPT target when DEBUG FSP is used
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch restructed MP init library so that more code can be
common between 32bit and 64bit. It is much easier to maintain the
code after the restructure.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enables QEMU SMM TSEG programming in FSP. And it also
enables SBL QEMU SMM rebasing. It can be used to test many SMM
related flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For appending Save/Restore structs in TSEG area,
bootloader should reserve space for TotalSize and
for certain structs, only header info should be
actually populated. Rest should be all Zeros.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Current SBL SMM rebasing check is only performed when PcdSmmRebaseMode
is enabled. It does not cover the case to boot UEFI payload. This patch
enhaced the check to cover UEFI payload S3 path as well.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When SMRR is enabled too early, it blocked TSEG access in Stage2.
And it caused S3 related issues. This patch delays the SMRR enabling
to be after PrePayloadLoading BoardInit().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For non UEFI payload, SBL will install dummy SMI handler for
security concern. For UEFI payload, SMM rebasing is expected
to be done itself. This patch enabled this feature for APL and
CFL platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In normal UEFI payload case, the UEFI will handle SMM rebasing.
If SMM rebasing is handled by SBL, SBL will put a dummy SMI handler
at the new SMBASE to prevent SMM hang. Beyond SMM rebasing, it
is also required to program SMRR registers. This patch added this
support for core code. It also added TSEG PCD init for CFL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will disable all PCI bus master by default, and enable it only if
- the original bus master was enabled before PCI enumeration
- Or the device is PCI Bridge
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL release debug output has more than what is expected.
This patch reset some of the debug message to proper level to limit
debug message for release build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented a common method for platform to create ACPI
table dynamically. Platform can provide ACPI tempalte array through
PCD PcdAcpiTableTemplatePtr. If provided, ACPI core code will try to
call platform code to patch the table, and then install the table to
ACPI RSDT/XSDT.
It also added sample code implementation in QEMU to show case how to
do it from platform code.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
GCC x64 build requires stack to be aligned at 16 bytes. In MpInit
nasm file, SBL set the initial stack to be 16-byte aligned. However,
later on unbalanced push/pop breaks the 16-byte alignment. This
patch removed extra stack pop so that the stack will always stay at
the original initial value.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PCI Enum Lib scopes for only Apperture resources
for a PPB. But some OSes (like ESXi) expect BAR0 & BAR1
(Offset 0x10/0x14) to be allocated resources accordingly.
Otherwise, PPB enumeration doesnt happen correctly and
devices behind PPB are not registered at all.
This patch adds the functionality to assign valid resources
to BAR0(0x10) and BAR1(0x14) for a PPB also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch removed duplicated X2APIC enabling code. Instead, it
enables X2APIC in a common function. By doing so, the very first
waking up will be done in APIC mode. Afterwards, it will be using
X2APIC mode if enabled by PCD.
This patch also fixed an X2APIC ACPI MADT issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.
X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
There is request to utilize MP in OsLoader. To support it, it is
desired to delay MP init done signal to the end of the OsLoader.
This patch moved the MP init done signal into board ReadyToBoot
notification so that MP is still alive in OsLoader phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This introduces an additional PCI Enumeration option.
- self._PCI_ENUM_FLAG_ALLOC_PMEM_FIRST
By deafult, the option will allocate PCI resource by ascending order
(MEM32->PMEM32->MEM64->PMEM64). If it's set to 1, by reversed order.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current PCI resource PCD bases are defined as fixed type. It
makes it impossible to dynamically adjust the base at runtime.
This patch changed it to be module patchable so that platform
can update when required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
BGRT can be used by bootloader to pass logo to OS. But BGRT can
only support 24bit or 32bit BMP format. If the bootloader uses
other bit format or indexed color format, the image has to be
converted before passing it to BGRT. This patch added support
to convert other BMP image format into 32bit format required by
BGRT.
This has been tested with Windows on Leafhill board. The SBL
logo was dispalyed properly while booting Windows.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
ProgramBar() routine uses 'OrgBarType' field to
determine BarType. So, if a BarType is valid, copy
it to OrgBarType for VF also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This introduces a new PCD 'PcdPciResAllocTableBase' to allow a platform
to provide its specific PCI resource allocation pool at runtime.
PCI Enumerator will allocate required resources in the range.
If the PCD is not provided, a default range will be used.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch enabled ACPI BGRT support. It is used to pass splash
display information from bootloader to payload and OS.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL code will build pointers in E/F segment for ACPI
and SMBIOS table. On some platforms, E/F segment is not supported.
So a new configuration ENABLE_LEGACY_EF_SEG is added. When
it is enabled, SBL will not use legacy E/F segment memory.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In 64-bit operation, some PCI devices have high mmio BARs,
but 32-bit FSP can only access 32-bit memory space.
This introduces and additional PCI resource downgrade option
to downgrade all PCI devices under Bus-0.
- self._PCI_ENUM_DOWNGRADE_BUS0 = 1
Force to have 32-bit BAR for all Bus-0 devices
Signed-off-by: Aiden Park <aiden.park@intel.com>
During X64 enabling, there was a pending task to enable 32bit
MultiBoot support. It is not implemented. This patch added the
support to allow X64 SBL to boot a 32bit MB image through thunking.
As part of this patch, the ThunkLib is separated from the FspApiLib
so that it can be shared by other component.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
All child devices under a PPB must be in scope of its PPB's decode space.
Therefore, all PPB checks the decode capability and downgrades its child
devices' resources accordingly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
The following commit 9fcb3a6be1
caused a regression on PCI bridge resource allocation. At minimum
the PCI bridge needs to have IO apperture aligned at 4KB and MMIO
apperture aligned at 1MB. The new code did not adjust the
alignment for P2P bridge following this rule. This patch fixed
this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Maurice Ma